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shader: Implement POPC

This commit is contained in:
ameerj 2021-02-26 21:41:46 -05:00
parent cc55d28949
commit a8c41c50d3
8 changed files with 59 additions and 12 deletions

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@ -69,6 +69,7 @@ add_library(shader_recompiler STATIC
frontend/maxwell/translate/impl/impl.cpp
frontend/maxwell/translate/impl/impl.h
frontend/maxwell/translate/impl/integer_add.cpp
frontend/maxwell/translate/impl/integer_popcount.cpp
frontend/maxwell/translate/impl/integer_scaled_add.cpp
frontend/maxwell/translate/impl/integer_set_predicate.cpp
frontend/maxwell/translate/impl/integer_shift_left.cpp

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@ -228,6 +228,8 @@ Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count)
Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
Id EmitBitReverse32(EmitContext& ctx, Id value);
Id EmitBitCount32(EmitContext& ctx, Id value);
Id EmitBitwiseNot32(EmitContext& ctx, Id a);
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);

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@ -106,6 +106,14 @@ Id EmitBitReverse32(EmitContext& ctx, Id value) {
return ctx.OpBitReverse(ctx.U32[1], value);
}
Id EmitBitCount32(EmitContext& ctx, Id value) {
return ctx.OpBitCount(ctx.U32[1], value);
}
Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
return ctx.OpNot(ctx.U32[1], a);
}
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSLessThan(ctx.U1, lhs, rhs);
}

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@ -808,6 +808,14 @@ U32 IREmitter::BitReverse(const U32& value) {
return Inst<U32>(Opcode::BitReverse32, value);
}
U32 IREmitter::BitCount(const U32& value) {
return Inst<U32>(Opcode::BitCount32, value);
}
U32 IREmitter::BitwiseNot(const U32& a) {
return Inst<U32>(Opcode::BitwiseNot32, a);
}
U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
}

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@ -160,6 +160,8 @@ public:
[[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
bool is_signed);
[[nodiscard]] U32 BitReverse(const U32& value);
[[nodiscard]] U32 BitCount(const U32& value);
[[nodiscard]] U32 BitwiseNot(const U32& a);
[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
[[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);

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@ -232,6 +232,8 @@ OPCODE(BitFieldInsert, U32, U32,
OPCODE(BitFieldSExtract, U32, U32, U32, U32, )
OPCODE(BitFieldUExtract, U32, U32, U32, U32, )
OPCODE(BitReverse32, U32, U32, )
OPCODE(BitCount32, U32, U32, )
OPCODE(BitwiseNot32, U32, U32, )
OPCODE(SLessThan, U1, U32, U32, )
OPCODE(ULessThan, U1, U32, U32, )

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@ -0,0 +1,36 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void POPC(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
union {
u64 raw;
BitField<0, 8, IR::Reg> dest_reg;
BitField<40, 1, u64> tilde;
} const popc{insn};
const IR::U32 operand = popc.tilde == 0 ? src : v.ir.BitwiseNot(src);
const IR::U32 result = v.ir.BitCount(operand);
v.X(popc.dest_reg, result);
}
} // Anonymous namespace
void TranslatorVisitor::POPC_reg(u64 insn) {
POPC(*this, insn, GetReg20(insn));
}
void TranslatorVisitor::POPC_cbuf(u64 insn) {
POPC(*this, insn, GetCbuf(insn));
}
void TranslatorVisitor::POPC_imm(u64 insn) {
POPC(*this, insn, GetImm20(insn));
}
} // namespace Shader::Maxwell

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@ -653,18 +653,6 @@ void TranslatorVisitor::PLONGJMP(u64) {
ThrowNotImplemented(Opcode::PLONGJMP);
}
void TranslatorVisitor::POPC_reg(u64) {
ThrowNotImplemented(Opcode::POPC_reg);
}
void TranslatorVisitor::POPC_cbuf(u64) {
ThrowNotImplemented(Opcode::POPC_cbuf);
}
void TranslatorVisitor::POPC_imm(u64) {
ThrowNotImplemented(Opcode::POPC_imm);
}
void TranslatorVisitor::PRET(u64) {
ThrowNotImplemented(Opcode::PRET);
}