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shader_ir/conversion: Implement F2I F16 Ra.H1

This commit is contained in:
ReinUsesLisp 2019-08-27 23:39:38 -03:00
parent b4a8cfbd00
commit b13fbc25b8
2 changed files with 17 additions and 6 deletions

View file

@ -1006,7 +1006,7 @@ union Instruction {
} iset; } iset;
union { union {
BitField<41, 2, u64> selector; // i2i and i2f only BitField<41, 2, u64> selector;
BitField<45, 1, u64> negate_a; BitField<45, 1, u64> negate_a;
BitField<49, 1, u64> abs_a; BitField<49, 1, u64> abs_a;
BitField<10, 2, Register::Size> src_size; BitField<10, 2, Register::Size> src_size;
@ -1031,7 +1031,6 @@ union Instruction {
return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask); return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
} }
} f2f; } f2f;
} conversion; } conversion;
union { union {

View file

@ -22,7 +22,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::I2I_R: case OpCode::Id::I2I_R:
case OpCode::Id::I2I_C: case OpCode::Id::I2I_C:
case OpCode::Id::I2I_IMM: { case OpCode::Id::I2I_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector); UNIMPLEMENTED_IF(instr.conversion.selector.Value());
UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word); UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
UNIMPLEMENTED_IF(instr.alu.saturate_d); UNIMPLEMENTED_IF(instr.alu.saturate_d);
@ -57,8 +57,8 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::I2F_R: case OpCode::Id::I2F_R:
case OpCode::Id::I2F_C: case OpCode::Id::I2F_C:
case OpCode::Id::I2F_IMM: { case OpCode::Id::I2F_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector.Value());
UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
UNIMPLEMENTED_IF(instr.conversion.selector);
UNIMPLEMENTED_IF_MSG(instr.generates_cc, UNIMPLEMENTED_IF_MSG(instr.generates_cc,
"Condition codes generation in I2F is not implemented"); "Condition codes generation in I2F is not implemented");
@ -93,6 +93,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::F2F_R: case OpCode::Id::F2F_R:
case OpCode::Id::F2F_C: case OpCode::Id::F2F_C:
case OpCode::Id::F2F_IMM: { case OpCode::Id::F2F_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector.Value());
UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
UNIMPLEMENTED_IF_MSG(instr.generates_cc, UNIMPLEMENTED_IF_MSG(instr.generates_cc,
@ -169,8 +170,19 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
}(); }();
if (instr.conversion.src_size == Register::Size::Short) { if (instr.conversion.src_size == Register::Size::Short) {
// TODO: figure where extract is sey in the encoding const OperationCode cast = [instr] {
value = Operation(OperationCode::FCastHalf0, PRECISE, value); switch (instr.conversion.selector) {
case 0:
return OperationCode::FCastHalf0;
case 1:
return OperationCode::FCastHalf1;
default:
UNREACHABLE_MSG("Invalid selector={}",
static_cast<u32>(instr.conversion.selector));
return OperationCode::FCastHalf0;
}
}();
value = Operation(cast, NO_PRECISE, std::move(value));
} }
value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a); value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);