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shader: Make IMNMX, SHR, SEL stylistically more consistent

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This commit is contained in:
ameerj 2021-03-01 00:25:15 -05:00
parent bce0b1dcca
commit bec7d3111d
3 changed files with 5 additions and 5 deletions
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2
src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
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@ -23,7 +23,7 @@ void IMNMX(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
throw NotImplementedException("IMNMX.MODE"); throw NotImplementedException("IMNMX.MODE");
} }
IR::U1 pred = v.ir.GetPred(imnmx.pred); IR::U1 pred{v.ir.GetPred(imnmx.pred)};
const IR::U32 op_a{v.X(imnmx.src_reg)}; const IR::U32 op_a{v.X(imnmx.src_reg)};
IR::U32 min; IR::U32 min;
IR::U32 max; IR::U32 max;

4
src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
View file

@ -16,7 +16,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
BitField<39, 1, u64> is_wrapped; BitField<39, 1, u64> is_wrapped;
BitField<40, 1, u64> brev; BitField<40, 1, u64> brev;
BitField<43, 1, u64> xmode; BitField<43, 1, u64> xmode;
BitField<48, 1, u64> is_arithmetic; BitField<48, 1, u64> is_signed;
} const shr{insn}; } const shr{insn};
if (shr.xmode != 0) { if (shr.xmode != 0) {
@ -29,7 +29,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
} }
IR::U32 result; IR::U32 result;
const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31)); const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
if (shr.is_arithmetic == 1) { if (shr.is_signed == 1) {
result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)}; result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
} else { } else {
result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)}; result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};

4
src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp
View file

@ -13,13 +13,13 @@ void SEL(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
union { union {
u64 raw; u64 raw;
BitField<0, 8, IR::Reg> dest_reg; BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> op_a; BitField<8, 8, IR::Reg> src_reg;
BitField<39, 3, IR::Pred> pred; BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred; BitField<42, 1, u64> neg_pred;
} const sel{insn}; } const sel{insn};
const IR::U1 pred = v.ir.GetPred(sel.pred); const IR::U1 pred = v.ir.GetPred(sel.pred);
IR::U32 op_a{v.X(sel.op_a)}; IR::U32 op_a{v.X(sel.src_reg)};
IR::U32 op_b{src}; IR::U32 op_b{src};
if (sel.neg_pred != 0) { if (sel.neg_pred != 0) {
std::swap(op_a, op_b); std::swap(op_a, op_b);