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VideoCore/Shader: Extract DebugData out from UnitState
This commit is contained in:
Yuri Kunde Schlesner
parent
6e7e767645
commit
c135317de1
8 changed files with 99 additions and 103 deletions
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@ -138,7 +138,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (immediate_attribute_id >= regs.vs.num_input_attributes + 1) {
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immediate_attribute_id = 0;
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Shader::UnitState<false> shader_unit;
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Shader::UnitState shader_unit;
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g_state.vs.Setup();
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// Send to vertex shader
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@ -237,7 +237,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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unsigned int vertex_cache_pos = 0;
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vertex_cache_ids.fill(-1);
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Shader::UnitState<false> shader_unit;
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Shader::UnitState shader_unit;
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g_state.vs.Setup();
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for (unsigned int index = 0; index < regs.num_vertices; ++index) {
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@ -19,8 +19,8 @@ struct DebugData;
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template <>
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struct DebugData<false> {
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// TODO: Hide these behind and interface and move them to DebugData<true>
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u32 max_offset; ///< maximum program counter ever reached
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u32 max_opdesc_id; ///< maximum swizzle pattern index ever used
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u32 max_offset = 0; ///< maximum program counter ever reached
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u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
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};
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template <>
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@ -75,8 +75,8 @@ struct DebugData<true> {
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unsigned mask = 0;
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};
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u32 max_offset; ///< maximum program counter ever reached
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u32 max_opdesc_id; ///< maximum swizzle pattern index ever used
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u32 max_offset = 0; ///< maximum program counter ever reached
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u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
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/// List of records for each executed shader instruction
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std::vector<DebugData<true>::Record> records;
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@ -109,15 +109,12 @@ void ShaderSetup::Setup() {
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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void ShaderSetup::Run(UnitState& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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MICROPROFILE_SCOPE(GPU_Shader);
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = config.input_register_map;
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@ -128,22 +125,23 @@ void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num
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state.conditional_code[1] = false;
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#ifdef ARCHITECTURE_x86_64
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if (VideoCore::g_shader_jit_enabled)
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if (VideoCore::g_shader_jit_enabled) {
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jit_shader->Run(setup, state, config.main_offset);
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else
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RunInterpreter(setup, state, config.main_offset);
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} else {
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DebugData<false> dummy_debug_data;
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RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
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}
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#else
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RunInterpreter(setup, state, config.main_offset);
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DebugData<false> dummy_debug_data;
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RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
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#endif // ARCHITECTURE_x86_64
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}
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DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes,
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const Regs::ShaderConfig& config,
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const ShaderSetup& setup) {
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UnitState<true> state;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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UnitState state;
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DebugData<true> debug_data;
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// Setup input register table
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boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero()));
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@ -154,8 +152,8 @@ DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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RunInterpreter(setup, state, config.main_offset);
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return state.debug;
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RunInterpreter(setup, state, debug_data, config.main_offset);
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return debug_data;
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}
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} // namespace Shader
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@ -94,7 +94,6 @@ static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
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* single shader unit that processes all shaders serially. Putting the state information in a struct
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* here will make it easier for us to parallelize the shader processing later.
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*/
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template <bool Debug>
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struct UnitState {
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struct Registers {
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// The registers are accessed by the shader JIT using SSE instructions, and are therefore
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@ -112,8 +111,6 @@ struct UnitState {
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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DebugData<Debug> debug;
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static size_t InputOffset(const SourceRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Input:
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@ -188,7 +185,7 @@ struct ShaderSetup {
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* @param input Input vertex into the shader
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* @param num_attributes The number of vertex shader attributes
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*/
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void Run(UnitState<false>& state, const InputVertex& input, int num_attributes);
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void Run(UnitState& state, const InputVertex& input, int num_attributes);
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/**
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* Produce debug information based on the given shader and input vertex
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@ -39,7 +39,8 @@ struct CallStackElement {
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};
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template <bool Debug>
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void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset) {
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void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
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unsigned offset) {
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// TODO: Is there a maximal size for this?
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boost::container::static_vector<CallStackElement, 16> call_stack;
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u32 program_counter = offset;
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@ -104,11 +105,11 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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const Instruction instr = {program_code[program_counter]};
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const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]};
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Record<DebugDataRecord::CUR_INSTR>(state.debug, iteration, program_counter);
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Record<DebugDataRecord::CUR_INSTR>(debug_data, iteration, program_counter);
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if (iteration > 0)
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Record<DebugDataRecord::NEXT_INSTR>(state.debug, iteration - 1, program_counter);
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Record<DebugDataRecord::NEXT_INSTR>(debug_data, iteration - 1, program_counter);
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + program_counter);
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debug_data.max_offset = std::max<u32>(debug_data.max_offset, 1 + program_counter);
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auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
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switch (source_reg.GetRegisterType()) {
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@ -176,54 +177,54 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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state.debug.max_opdesc_id =
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std::max<u32>(state.debug.max_opdesc_id, 1 + instr.common.operand_desc_id);
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debug_data.max_opdesc_id =
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std::max<u32>(debug_data.max_opdesc_id, 1 + instr.common.operand_desc_id);
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switch (instr.opcode.Value().EffectiveOpCode()) {
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case OpCode::Id::ADD: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] + src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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case OpCode::Id::MUL: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] * src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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case OpCode::Id::FLR:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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case OpCode::Id::MAX:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -233,13 +234,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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// max(NaN, 0) -> 0
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dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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case OpCode::Id::MIN:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -249,16 +250,16 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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// min(NaN, 0) -> 0
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dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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case OpCode::Id::DP3:
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case OpCode::Id::DP4:
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case OpCode::Id::DPH:
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case OpCode::Id::DPHI: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
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if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
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@ -274,14 +275,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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dest[i] = dot;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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// Reciprocal
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case OpCode::Id::RCP: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -289,14 +290,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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dest[i] = rcp_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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// Reciprocal Square Root
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case OpCode::Id::RSQ: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -304,12 +305,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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dest[i] = rsq_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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case OpCode::Id::MOVA: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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for (int i = 0; i < 2; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -317,29 +318,29 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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// TODO: Figure out how the rounding is done on hardware
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state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
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}
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Record<DebugDataRecord::ADDR_REG_OUT>(state.debug, iteration,
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Record<DebugDataRecord::ADDR_REG_OUT>(debug_data, iteration,
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state.address_registers);
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break;
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}
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case OpCode::Id::MOV: {
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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}
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case OpCode::Id::SGE:
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case OpCode::Id::SGEI:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -347,14 +348,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f)
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: float24::FromFloat32(0.0f);
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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case OpCode::Id::SLT:
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case OpCode::Id::SLTI:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
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Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -362,12 +363,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f)
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: float24::FromFloat32(0.0f);
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
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break;
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case OpCode::Id::CMP:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
||||
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
// TODO: Can you restrict to one compare via dest masking?
|
||||
|
||||
|
|
@ -404,12 +405,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
break;
|
||||
}
|
||||
}
|
||||
Record<DebugDataRecord::CMP_RESULT>(state.debug, iteration, state.conditional_code);
|
||||
Record<DebugDataRecord::CMP_RESULT>(debug_data, iteration, state.conditional_code);
|
||||
break;
|
||||
|
||||
case OpCode::Id::EX2: {
|
||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||
|
||||
// EX2 only takes first component exp2 and writes it to all dest components
|
||||
float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
|
||||
|
|
@ -420,13 +421,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
dest[i] = ex2_res;
|
||||
}
|
||||
|
||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||
break;
|
||||
}
|
||||
|
||||
case OpCode::Id::LG2: {
|
||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||
|
||||
// LG2 only takes the first component log2 and writes it to all dest components
|
||||
float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
|
||||
|
|
@ -437,7 +438,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
dest[i] = lg2_res;
|
||||
}
|
||||
|
||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -519,17 +520,17 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
|
||||
: dummy_vec4_float24;
|
||||
|
||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
||||
Record<DebugDataRecord::SRC3>(state.debug, iteration, src3);
|
||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||
Record<DebugDataRecord::SRC3>(debug_data, iteration, src3);
|
||||
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
if (!swizzle.DestComponentEnabled(i))
|
||||
continue;
|
||||
|
||||
dest[i] = src1[i] * src2[i] + src3[i];
|
||||
}
|
||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
||||
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||
} else {
|
||||
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
|
||||
(int)instr.opcode.Value().EffectiveOpCode(),
|
||||
|
|
@ -546,8 +547,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
break;
|
||||
|
||||
case OpCode::Id::JMPC:
|
||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
||||
state.conditional_code);
|
||||
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||
if (evaluate_condition(instr.flow_control)) {
|
||||
program_counter = instr.flow_control.dest_offset - 1;
|
||||
}
|
||||
|
|
@ -555,7 +555,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
|
||||
case OpCode::Id::JMPU:
|
||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
|
||||
if (uniforms.b[instr.flow_control.bool_uniform_id] ==
|
||||
!(instr.flow_control.num_instructions & 1)) {
|
||||
|
|
@ -570,7 +570,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
|
||||
case OpCode::Id::CALLU:
|
||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||
program_counter + 1, 0, 0);
|
||||
|
|
@ -578,8 +578,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
break;
|
||||
|
||||
case OpCode::Id::CALLC:
|
||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
||||
state.conditional_code);
|
||||
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||
if (evaluate_condition(instr.flow_control)) {
|
||||
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||
program_counter + 1, 0, 0);
|
||||
|
|
@ -591,7 +590,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
|
||||
case OpCode::Id::IFU:
|
||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||
|
|
@ -607,8 +606,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
case OpCode::Id::IFC: {
|
||||
// TODO: Do we need to consider swizzlers here?
|
||||
|
||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
||||
state.conditional_code);
|
||||
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||
if (evaluate_condition(instr.flow_control)) {
|
||||
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||
|
|
@ -629,7 +627,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
uniforms.i[instr.flow_control.int_uniform_id].w);
|
||||
state.address_registers[2] = loop_param.y;
|
||||
|
||||
Record<DebugDataRecord::LOOP_INT_IN>(state.debug, iteration, loop_param);
|
||||
Record<DebugDataRecord::LOOP_INT_IN>(debug_data, iteration, loop_param);
|
||||
call(program_counter + 1, instr.flow_control.dest_offset - program_counter + 1,
|
||||
instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z);
|
||||
break;
|
||||
|
|
@ -652,8 +650,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||
}
|
||||
|
||||
// Explicit instantiation
|
||||
template void RunInterpreter(const ShaderSetup& setup, UnitState<false>& state, unsigned offset);
|
||||
template void RunInterpreter(const ShaderSetup& setup, UnitState<true>& state, unsigned offset);
|
||||
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<false>&, unsigned offset);
|
||||
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<true>&, unsigned offset);
|
||||
|
||||
} // namespace
|
||||
|
||||
|
|
|
|||
|
|
@ -8,11 +8,14 @@ namespace Pica {
|
|||
|
||||
namespace Shader {
|
||||
|
||||
template <bool Debug>
|
||||
struct UnitState;
|
||||
|
||||
template <bool Debug>
|
||||
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset);
|
||||
struct DebugData;
|
||||
|
||||
template <bool Debug>
|
||||
void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
|
||||
unsigned offset);
|
||||
|
||||
} // namespace
|
||||
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
|
|||
src_offset = ShaderSetup::GetFloatUniformOffset(src_reg.GetIndex());
|
||||
} else {
|
||||
src_ptr = STATE;
|
||||
src_offset = UnitState<false>::InputOffset(src_reg);
|
||||
src_offset = UnitState::InputOffset(src_reg);
|
||||
}
|
||||
|
||||
int src_offset_disp = (int)src_offset;
|
||||
|
|
@ -266,7 +266,7 @@ void JitShader::Compile_DestEnable(Instruction instr, Xmm src) {
|
|||
|
||||
SwizzlePattern swiz = {g_state.vs.swizzle_data[operand_desc_id]};
|
||||
|
||||
size_t dest_offset_disp = UnitState<false>::OutputOffset(dest);
|
||||
size_t dest_offset_disp = UnitState::OutputOffset(dest);
|
||||
|
||||
// If all components are enabled, write the result to the destination register
|
||||
if (swiz.dest_mask == NO_DEST_REG_MASK) {
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ class JitShader : public Xbyak::CodeGenerator {
|
|||
public:
|
||||
JitShader();
|
||||
|
||||
void Run(const ShaderSetup& setup, UnitState<false>& state, unsigned offset) const {
|
||||
void Run(const ShaderSetup& setup, UnitState& state, unsigned offset) const {
|
||||
program(&setup, &state, instruction_labels[offset].getAddress());
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue