mirrors/yuzu
2
1
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-07-04 23:31:19 +01:00
Code Issues Releases Activity

spirv: Fix implicit lod type

Browse source
This commit is contained in:
ReinUsesLisp 2021-04-17 03:19:54 -03:00 committed by ameerj
parent 7cfa403683
commit c9e4609d87
2 changed files with 5 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/shader_recompiler/backend/spirv/emit_context.h
View file

@ -101,6 +101,10 @@ public:
return Constant(U32[1], value); return Constant(U32[1], value);
} }
Id Const(f32 value) {
return Constant(F32[1], value);
}
Id Const(u32 element_1, u32 element_2) { Id Const(u32 element_1, u32 element_2) {
return ConstantComposite(U32[2], Const(element_1), Const(element_2)); return ConstantComposite(U32[2], Const(element_1), Const(element_2));
} }

2
src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
View file

@ -320,7 +320,7 @@ Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value&
// We can't use implicit lods on non-fragment stages on SPIR-V. Maxwell hardware behaves as // We can't use implicit lods on non-fragment stages on SPIR-V. Maxwell hardware behaves as
// if the lod was explicitly zero. This may change on Turing with implicit compute // if the lod was explicitly zero. This may change on Turing with implicit compute
// derivatives // derivatives
const Id lod{ctx.Const(0)}; const Id lod{ctx.Const(0.0f)};
const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod, offset); const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod, offset);
return Emit(&EmitContext::OpImageSparseSampleExplicitLod, return Emit(&EmitContext::OpImageSparseSampleExplicitLod,
&EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4], &EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4],