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Code Issues Releases Activity

arithmetic_integer_immediate: Make use of std::move where applicable

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Same behavior, minus any redundant atomic reference count increments and
decrements.
This commit is contained in:
Lioncash 2020-09-24 13:21:22 -04:00
parent 2b863c9aa3
commit e3a615a616
1 changed files with 19 additions and 16 deletions
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35
src/video_core/shader/decode/arithmetic_integer_immediate.cpp
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@ -28,23 +28,26 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
case OpCode::Id::IADD32I: { case OpCode::Id::IADD32I: {
UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented"); UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented");
op_a = GetOperandAbsNegInteger(op_a, false, instr.iadd32i.negate_a, true); op_a = GetOperandAbsNegInteger(std::move(op_a), false, instr.iadd32i.negate_a != 0, true);
const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b); Node value = Operation(OperationCode::IAdd, PRECISE, std::move(op_a), std::move(op_b));
SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc); SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc != 0);
SetRegister(bb, instr.gpr0, value); SetRegister(bb, instr.gpr0, std::move(value));
break; break;
} }
case OpCode::Id::LOP32I: { case OpCode::Id::LOP32I: {
if (instr.alu.lop32i.invert_a) if (instr.alu.lop32i.invert_a) {
op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a); op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_a));
}
if (instr.alu.lop32i.invert_b) if (instr.alu.lop32i.invert_b) {
op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_b));
}
WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, op_a, op_b, WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, std::move(op_a),
PredicateResultMode::None, Pred::UnusedIndex, instr.op_32.generates_cc); std::move(op_b), PredicateResultMode::None, Pred::UnusedIndex,
instr.op_32.generates_cc != 0);
break; break;
} }
default: default:
@ -58,14 +61,14 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a, void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a,
Node op_b, PredicateResultMode predicate_mode, Pred predicate, Node op_b, PredicateResultMode predicate_mode, Pred predicate,
bool sets_cc) { bool sets_cc) {
const Node result = [&]() { Node result = [&] {
switch (logic_op) { switch (logic_op) {
case LogicOperation::And: case LogicOperation::And:
return Operation(OperationCode::IBitwiseAnd, PRECISE, op_a, op_b); return Operation(OperationCode::IBitwiseAnd, PRECISE, std::move(op_a), std::move(op_b));
case LogicOperation::Or: case LogicOperation::Or:
return Operation(OperationCode::IBitwiseOr, PRECISE, op_a, op_b); return Operation(OperationCode::IBitwiseOr, PRECISE, std::move(op_a), std::move(op_b));
case LogicOperation::Xor: case LogicOperation::Xor:
return Operation(OperationCode::IBitwiseXor, PRECISE, op_a, op_b); return Operation(OperationCode::IBitwiseXor, PRECISE, std::move(op_a), std::move(op_b));
case LogicOperation::PassB: case LogicOperation::PassB:
return op_b; return op_b;
default: default:
@ -84,8 +87,8 @@ void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation
return; return;
case PredicateResultMode::NotZero: { case PredicateResultMode::NotZero: {
// Set the predicate to true if the result is not zero. // Set the predicate to true if the result is not zero.
const Node compare = Operation(OperationCode::LogicalINotEqual, result, Immediate(0)); Node compare = Operation(OperationCode::LogicalINotEqual, std::move(result), Immediate(0));
SetPredicate(bb, static_cast<u64>(predicate), compare); SetPredicate(bb, static_cast<u64>(predicate), std::move(compare));
break; break;
} }
default: default: