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125caf5d6e
This allows the implementation of these types to change without requiring a rebuild of everything that includes the macro interpreter header.
109 lines
3.3 KiB
C++
109 lines
3.3 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D;
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}
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class MacroInterpreter final {
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public:
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explicit MacroInterpreter(Engines::Maxwell3D& maxwell3d);
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/**
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* Executes the macro code with the specified input parameters.
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* @param offset Offset to start execution at.
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* @param parameters The parameters of the macro.
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*/
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void Execute(u32 offset, std::size_t num_parameters, const u32* parameters);
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private:
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enum class ALUOperation : u32;
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enum class BranchCondition : u32;
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enum class ResultOperation : u32;
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union Opcode;
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union MethodAddress {
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u32 raw;
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BitField<0, 12, u32> address;
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BitField<12, 6, u32> increment;
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};
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/// Resets the execution engine state, zeroing registers, etc.
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void Reset();
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/**
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* Executes a single macro instruction located at the current program counter. Returns whether
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* the interpreter should keep running.
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* @param offset Offset to start execution at.
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* @param is_delay_slot Whether the current step is being executed due to a delay slot in a
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* previous instruction.
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*/
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bool Step(u32 offset, bool is_delay_slot);
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/// Calculates the result of an ALU operation. src_a OP src_b;
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u32 GetALUResult(ALUOperation operation, u32 src_a, u32 src_b);
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/// Performs the result operation on the input result and stores it in the specified register
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/// (if necessary).
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void ProcessResult(ResultOperation operation, u32 reg, u32 result);
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/// Evaluates the branch condition and returns whether the branch should be taken or not.
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bool EvaluateBranchCondition(BranchCondition cond, u32 value) const;
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/// Reads an opcode at the current program counter location.
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Opcode GetOpcode(u32 offset) const;
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/// Returns the specified register's value. Register 0 is hardcoded to always return 0.
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u32 GetRegister(u32 register_id) const;
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/// Sets the register to the input value.
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void SetRegister(u32 register_id, u32 value);
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/// Sets the method address to use for the next Send instruction.
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void SetMethodAddress(u32 address);
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/// Calls a GPU Engine method with the input parameter.
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void Send(u32 value);
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/// Reads a GPU register located at the method address.
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u32 Read(u32 method) const;
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/// Returns the next parameter in the parameter queue.
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u32 FetchParameter();
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Engines::Maxwell3D& maxwell3d;
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/// Current program counter
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u32 pc;
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/// Program counter to execute at after the delay slot is executed.
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std::optional<u32> delayed_pc;
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static constexpr std::size_t NumMacroRegisters = 8;
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/// General purpose macro registers.
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std::array<u32, NumMacroRegisters> registers = {};
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/// Method address to use for the next Send instruction.
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MethodAddress method_address = {};
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/// Input parameters of the current macro.
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std::unique_ptr<u32[]> parameters;
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std::size_t num_parameters = 0;
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std::size_t parameters_capacity = 0;
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/// Index of the next parameter that will be fetched by the 'parm' instruction.
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u32 next_parameter_index = 0;
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bool carry_flag = false;
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};
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} // namespace Tegra
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