mirror of
https://github.com/HamletDuFromage/aio-switch-updater.git
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107 lines
4.1 KiB
C
107 lines
4.1 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <soc/ccplex.h>
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#include <soc/i2c.h>
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#include <soc/clock.h>
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#include <soc/pmc.h>
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#include <soc/t210.h>
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#include <power/max77620.h>
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#include <power/max7762x.h>
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#include <utils/util.h>
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void _ccplex_enable_power()
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{
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u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~(1 << 5)); // Disable GPIO5 pinmuxing.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
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// Enable cores power.
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// 1-3.x: MAX77621_NFSR_ENABLE.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
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MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE | MAX77621_RAMP_12mV_PER_US);
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// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
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}
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void ccplex_boot_cpu0(u32 entry)
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{
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// Set ACTIVE_CLUSER to FAST.
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FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
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_ccplex_enable_power();
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
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{
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
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}
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
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;
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// Configure MSELECT source and enable clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & ~BIT(CLK_V_MSELECT)) | BIT(CLK_V_MSELECT);
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// Configure initial CPU clock frequency and enable clock.
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CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
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CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG);
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clock_enable_coresight();
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// CAR2PMC_CPU_ACK_WIDTH should be set to 0.
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CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
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// Enable CPU rail.
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pmc_enable_partition(0, 1);
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// Enable cluster 0 non-CPU rail.
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pmc_enable_partition(15, 1);
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// Enable CE0 rail.
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pmc_enable_partition(14, 1);
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// Request and wait for RAM repair.
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FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
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while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
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;
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EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0;
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// Set reset vector.
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SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN;
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SB(SB_AA64_RESET_HIGH) = 0;
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// Non-secure reset vector write disable.
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SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
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(void)SB(SB_CSR);
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// Tighten up the security aperture.
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// MC(MC_TZ_SECURITY_CTRL) = 1;
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// Clear MSELECT reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= ~BIT(CLK_V_MSELECT);
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// Clear NONCPU reset.
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
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// Clear CPU0 reset.
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// < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001;
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}
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