2020-06-11 09:30:30 +01:00
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/*
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2021-10-04 20:59:10 +01:00
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* Copyright (c) Atmosphère-NX
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2020-06-11 09:30:30 +01:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "warmboot_clkrst.hpp"
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namespace ams::warmboot {
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namespace {
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constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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constexpr inline const uintptr_t EMC = EMC_ADDRESS(0);
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}
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void ApplyMbistWorkaround() {
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/* Clear all LVL2 clock gate overrides to zero. */
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reg::Write(CLKRST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA, 0);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB, 0);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC, 0);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD, 0);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE, 0);
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/* Clear clock enable for all but a select few devices. */
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auto devices_to_clear_l = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_L);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_l), CLK_RST_REG_BITS_MASK(CLK_ENB_L_CLK_ENB_RTC ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_L_CLK_ENB_TMR ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_L_CLK_ENB_GPIO ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_L_CLK_ENB_CACHE2));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, devices_to_clear_l);
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auto devices_to_clear_h = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_H);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_h), CLK_RST_REG_BITS_MASK(CLK_ENB_H_CLK_ENB_MEM ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_H_CLK_ENB_PMC ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_H_CLK_ENB_FUSE),
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CLK_RST_REG_BITS_MASK(CLK_ENB_H_CLK_ENB_EMC ));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, devices_to_clear_h);
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auto devices_to_clear_u = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_U);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_u), CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_CSITE),
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CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_IRAMA),
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CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_IRAMB),
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CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_IRAMC),
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CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_IRAMD),
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CLK_RST_REG_BITS_MASK(CLK_ENB_U_CLK_ENB_CRAM2));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_U_CLR, devices_to_clear_u);
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auto devices_to_clear_v = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_V);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_v), CLK_RST_REG_BITS_MASK(CLK_ENB_V_CLK_ENB_MSELECT ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_V_CLK_ENB_SPDIF_DOUBLER),
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CLK_RST_REG_BITS_MASK(CLK_ENB_V_CLK_ENB_TZRAM ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_V_CLK_ENB_SE ));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_V_CLR, devices_to_clear_v);
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auto devices_to_clear_w = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_W);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_w), CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX0),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX1),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX2),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX3),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX4),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_PCIERX5),
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CLK_RST_REG_BITS_MASK(CLK_ENB_W_CLK_ENB_ENTROPY));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_W_CLR, devices_to_clear_w);
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auto devices_to_clear_x = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_X);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_x), CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_MC_CAPA ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_MC_CBPA ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_MC_CPU ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_MC_BBC ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_EMC_DLL ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_GPU ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_DBGAPB ),
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CLK_RST_REG_BITS_MASK(CLK_ENB_X_CLK_ENB_PLLG_REF));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_X_CLR, devices_to_clear_x);
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auto devices_to_clear_y = reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_OUT_ENB_Y);
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reg::ClearBits(static_cast<volatile u32 &>(devices_to_clear_y), CLK_RST_REG_BITS_MASK(CLK_ENB_Y_CLK_ENB_MC_CCPA),
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CLK_RST_REG_BITS_MASK(CLK_ENB_Y_CLK_ENB_MC_CDPA));
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_Y_CLR, devices_to_clear_y);
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/* If CH1 is enabled, enable clock to MC1. */
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if (reg::HasValue(EMC + EMC_FBIO_CFG7, EMC_REG_BITS_ENUM(FBIO_CFG7_CH1_ENABLE, ENABLE))) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_W_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_W_CLK_ENB_MC1, ENABLE));
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}
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}
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}
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