2018-09-07 16:00:13 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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2019-04-08 03:00:49 +01:00
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* Copyright (c) 2018-2019 Atmosphère-NX
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2018-09-07 16:00:13 +01:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-08-18 17:59:33 +01:00
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#ifndef FUSEE_TSEC_H_
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#define FUSEE_TSEC_H_
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#include <string.h>
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#include <stdbool.h>
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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2019-12-31 17:59:15 +00:00
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#define KFUSE_BASE 0x7000FC00
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2018-08-18 17:59:33 +01:00
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#define SOR1_DP_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x1E8)
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#define SOR1_TMDS_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x21C)
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#define SOR1_TMDS_HDCP_CN_MSB MAKE_REG32(SOR1_BASE + 0x208)
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#define SOR1_TMDS_HDCP_CN_LSB MAKE_REG32(SOR1_BASE + 0x20C)
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2019-12-31 17:59:15 +00:00
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#define KFUSE_FUSECTRL MAKE_REG32(KFUSE_BASE + 0x00)
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#define KFUSE_FUSEADDR MAKE_REG32(KFUSE_BASE + 0x04)
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#define KFUSE_FUSEDATA0 MAKE_REG32(KFUSE_BASE + 0x08)
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#define KFUSE_FUSEWRDATA0 MAKE_REG32(KFUSE_BASE + 0x0C)
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#define KFUSE_FUSETIME_RD1 MAKE_REG32(KFUSE_BASE + 0x10)
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#define KFUSE_FUSETIME_RD2 MAKE_REG32(KFUSE_BASE + 0x14)
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#define KFUSE_FUSETIME_PGM1 MAKE_REG32(KFUSE_BASE + 0x18)
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#define KFUSE_FUSETIME_PGM2 MAKE_REG32(KFUSE_BASE + 0x1C)
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#define KFUSE_REGULATOR MAKE_REG32(KFUSE_BASE + 0x20)
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#define KFUSE_PD MAKE_REG32(KFUSE_BASE + 0x24)
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#define KFUSE_FUSETIME_RD3 MAKE_REG32(KFUSE_BASE + 0x28)
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#define KFUSE_STATE MAKE_REG32(KFUSE_BASE + 0x80)
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#define KFUSE_ERRCOUNT MAKE_REG32(KFUSE_BASE + 0x84)
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#define KFUSE_KEYADDR MAKE_REG32(KFUSE_BASE + 0x88)
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#define KFUSE_KEYS MAKE_REG32(KFUSE_BASE + 0x8C)
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2018-08-18 17:59:33 +01:00
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typedef struct {
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2019-12-31 17:59:15 +00:00
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uint32_t TSEC_THI_INCR_SYNCPT; /* Tegra Host Interface registers. */
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uint32_t TSEC_THI_INCR_SYNCPT_CTRL;
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uint32_t TSEC_THI_INCR_SYNCPT_ERR;
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uint32_t TSEC_THI_CTXSW_INCR_SYNCPT;
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uint32_t _0x10[0x4];
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uint32_t TSEC_THI_CTXSW;
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uint32_t TSEC_THI_CTXSW_NEXT;
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uint32_t TSEC_THI_CONT_SYNCPT_EOF;
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uint32_t TSEC_THI_CONT_SYNCPT_L1;
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uint32_t TSEC_THI_STREAMID0;
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uint32_t TSEC_THI_STREAMID1;
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uint32_t TSEC_THI_THI_SEC;
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uint32_t _0x3C;
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uint32_t TSEC_THI_METHOD0;
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uint32_t TSEC_THI_METHOD1;
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uint32_t _0x48[0x6];
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uint32_t TSEC_THI_CONTEXT_SWITCH;
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uint32_t _0x64[0x5];
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uint32_t TSEC_THI_INT_STATUS;
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uint32_t TSEC_THI_INT_MASK;
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uint32_t TSEC_THI_CONFIG0;
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uint32_t TSEC_THI_DBG_MISC;
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uint32_t TSEC_THI_SLCG_OVERRIDE_HIGH_A;
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uint32_t TSEC_THI_SLCG_OVERRIDE_LOW_A;
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uint32_t _0x90[0x35C];
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uint32_t TSEC_THI_CLK_OVERRIDE;
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uint32_t _0xE04[0x7F];
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uint32_t TSEC_FALCON_IRQSSET; /* Falcon microcontroller registers. */
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uint32_t TSEC_FALCON_IRQSCLR;
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uint32_t TSEC_FALCON_IRQSTAT;
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uint32_t TSEC_FALCON_IRQMODE;
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uint32_t TSEC_FALCON_IRQMSET;
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uint32_t TSEC_FALCON_IRQMCLR;
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uint32_t TSEC_FALCON_IRQMASK;
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uint32_t TSEC_FALCON_IRQDEST;
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uint32_t TSEC_FALCON_GPTMRINT;
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uint32_t TSEC_FALCON_GPTMRVAL;
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uint32_t TSEC_FALCON_GPTMRCTL;
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uint32_t TSEC_FALCON_PTIMER0;
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uint32_t TSEC_FALCON_PTIMER1;
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uint32_t TSEC_FALCON_WDTMRVAL;
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uint32_t TSEC_FALCON_WDTMRCTL;
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uint32_t TSEC_FALCON_IRQDEST2;
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uint32_t TSEC_FALCON_MAILBOX0;
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uint32_t TSEC_FALCON_MAILBOX1;
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uint32_t TSEC_FALCON_ITFEN;
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uint32_t TSEC_FALCON_IDLESTATE;
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uint32_t TSEC_FALCON_CURCTX;
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uint32_t TSEC_FALCON_NXTCTX;
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uint32_t TSEC_FALCON_CTXACK;
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uint32_t TSEC_FALCON_FHSTATE;
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uint32_t TSEC_FALCON_PRIVSTATE;
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uint32_t TSEC_FALCON_MTHDDATA;
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uint32_t TSEC_FALCON_MTHDID;
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uint32_t TSEC_FALCON_MTHDWDAT;
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uint32_t TSEC_FALCON_MTHDCOUNT;
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uint32_t TSEC_FALCON_MTHDPOP;
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uint32_t TSEC_FALCON_MTHDRAMSZ;
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uint32_t TSEC_FALCON_SFTRESET;
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uint32_t TSEC_FALCON_OS;
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uint32_t TSEC_FALCON_RM;
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uint32_t TSEC_FALCON_SOFT_PM;
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uint32_t TSEC_FALCON_SOFT_MODE;
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uint32_t TSEC_FALCON_DEBUG1;
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uint32_t TSEC_FALCON_DEBUGINFO;
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uint32_t TSEC_FALCON_IBRKPT1;
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uint32_t TSEC_FALCON_IBRKPT2;
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uint32_t TSEC_FALCON_CGCTL;
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uint32_t TSEC_FALCON_ENGCTL;
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uint32_t TSEC_FALCON_PMM;
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uint32_t TSEC_FALCON_ADDR;
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uint32_t TSEC_FALCON_IBRKPT3;
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uint32_t TSEC_FALCON_IBRKPT4;
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uint32_t TSEC_FALCON_IBRKPT5;
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uint32_t _0x10BC[0x5];
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uint32_t TSEC_FALCON_EXCI;
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uint32_t TSEC_FALCON_SVEC_SPR;
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uint32_t TSEC_FALCON_RSTAT0;
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uint32_t TSEC_FALCON_RSTAT3;
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uint32_t _0x10E0[0x8];
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uint32_t TSEC_FALCON_CPUCTL;
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uint32_t TSEC_FALCON_BOOTVEC;
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uint32_t TSEC_FALCON_HWCFG;
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uint32_t TSEC_FALCON_DMACTL;
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uint32_t TSEC_FALCON_DMATRFBASE;
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uint32_t TSEC_FALCON_DMATRFMOFFS;
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uint32_t TSEC_FALCON_DMATRFCMD;
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uint32_t TSEC_FALCON_DMATRFFBOFFS;
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uint32_t TSEC_FALCON_DMAPOLL_FB;
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uint32_t TSEC_FALCON_DMAPOLL_CP;
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uint32_t TSEC_FALCON_DBG_STATE;
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uint32_t TSEC_FALCON_HWCFG1;
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uint32_t TSEC_FALCON_CPUCTL_ALIAS;
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uint32_t _0x1134;
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uint32_t TSEC_FALCON_STACKCFG;
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uint32_t _0x113C;
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uint32_t TSEC_FALCON_IMCTL;
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uint32_t TSEC_FALCON_IMSTAT;
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uint32_t TSEC_FALCON_TRACEIDX;
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uint32_t TSEC_FALCON_TRACEPC;
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uint32_t TSEC_FALCON_IMFILLRNG0;
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uint32_t TSEC_FALCON_IMFILLRNG1;
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uint32_t TSEC_FALCON_IMFILLCTL;
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uint32_t TSEC_FALCON_IMCTL_DEBUG;
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uint32_t TSEC_FALCON_CMEMBASE;
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uint32_t TSEC_FALCON_DMEMAPERT;
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uint32_t TSEC_FALCON_EXTERRADDR;
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uint32_t TSEC_FALCON_EXTERRSTAT;
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uint32_t _0x1170[0x3];
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uint32_t TSEC_FALCON_CG2;
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uint32_t TSEC_FALCON_IMEMC0;
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uint32_t TSEC_FALCON_IMEMD0;
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uint32_t TSEC_FALCON_IMEMT0;
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uint32_t _0x118C;
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uint32_t TSEC_FALCON_IMEMC1;
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uint32_t TSEC_FALCON_IMEMD1;
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uint32_t TSEC_FALCON_IMEMT1;
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uint32_t _0x119C;
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uint32_t TSEC_FALCON_IMEMC2;
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uint32_t TSEC_FALCON_IMEMD2;
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uint32_t TSEC_FALCON_IMEMT2;
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uint32_t _0x11AC;
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uint32_t TSEC_FALCON_IMEMC3;
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uint32_t TSEC_FALCON_IMEMD3;
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uint32_t TSEC_FALCON_IMEMT3;
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uint32_t _0x11BC;
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uint32_t TSEC_FALCON_DMEMC0;
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uint32_t TSEC_FALCON_DMEMD0;
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uint32_t TSEC_FALCON_DMEMC1;
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uint32_t TSEC_FALCON_DMEMD1;
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uint32_t TSEC_FALCON_DMEMC2;
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uint32_t TSEC_FALCON_DMEMD2;
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uint32_t TSEC_FALCON_DMEMC3;
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uint32_t TSEC_FALCON_DMEMD3;
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uint32_t TSEC_FALCON_DMEMC4;
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uint32_t TSEC_FALCON_DMEMD4;
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uint32_t TSEC_FALCON_DMEMC5;
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uint32_t TSEC_FALCON_DMEMD5;
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uint32_t TSEC_FALCON_DMEMC6;
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uint32_t TSEC_FALCON_DMEMD6;
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uint32_t TSEC_FALCON_DMEMC7;
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uint32_t TSEC_FALCON_DMEMD7;
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uint32_t TSEC_FALCON_ICD_CMD;
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uint32_t TSEC_FALCON_ICD_ADDR;
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uint32_t TSEC_FALCON_ICD_WDATA;
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uint32_t TSEC_FALCON_ICD_RDATA;
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uint32_t _0x1210[0xC];
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uint32_t TSEC_FALCON_SCTL;
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uint32_t TSEC_FALCON_SSTAT;
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uint32_t _0x1248[0xE];
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uint32_t TSEC_FALCON_SPROT_IMEM;
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uint32_t TSEC_FALCON_SPROT_DMEM;
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uint32_t TSEC_FALCON_SPROT_CPUCTL;
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uint32_t TSEC_FALCON_SPROT_MISC;
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uint32_t TSEC_FALCON_SPROT_IRQ;
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uint32_t TSEC_FALCON_SPROT_MTHD;
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uint32_t TSEC_FALCON_SPROT_SCTL;
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uint32_t TSEC_FALCON_SPROT_WDTMR;
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uint32_t _0x12A0[0x8];
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uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW;
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uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH;
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uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW;
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uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH;
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uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW;
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uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH;
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uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW;
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uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH;
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uint32_t TSEC_FALCON_DMAINFO_CTL;
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uint32_t _0x12E4[0x47];
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uint32_t TSEC_SCP_CTL0; /* Secure Co-processor registers. */
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uint32_t TSEC_SCP_CTL1;
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uint32_t TSEC_SCP_CTL_STAT;
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uint32_t TSEC_SCP_CTL_LOCK;
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uint32_t TSEC_SCP_CFG;
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uint32_t TSEC_SCP_CTL_SCP;
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uint32_t TSEC_SCP_CTL_PKEY;
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uint32_t TSEC_SCP_CTL_DBG;
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uint32_t TSEC_SCP_DBG0;
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uint32_t TSEC_SCP_DBG1;
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uint32_t TSEC_SCP_DBG2;
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uint32_t _0x142C;
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uint32_t TSEC_SCP_CMD;
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uint32_t _0x1434[0x7];
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uint32_t TSEC_SCP_STAT0;
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uint32_t TSEC_SCP_STAT1;
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uint32_t TSEC_SCP_STAT2;
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uint32_t _0x145C[0x5];
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uint32_t TSEC_SCP_RND_STAT0;
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uint32_t TSEC_SCP_RND_STAT1;
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uint32_t _0x1478[0x2];
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uint32_t TSEC_SCP_IRQSTAT;
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uint32_t TSEC_SCP_IRQMASK;
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uint32_t _0x1488[0x2];
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uint32_t TSEC_SCP_ACL_ERR;
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uint32_t TSEC_SCP_SEC_ERR;
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uint32_t TSEC_SCP_CMD_ERR;
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uint32_t _0x149C[0x19];
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uint32_t TSEC_RND_CTL0; /* Random Number Generator registers. */
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uint32_t TSEC_RND_CTL1;
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uint32_t TSEC_RND_CTL2;
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uint32_t TSEC_RND_CTL3;
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uint32_t TSEC_RND_CTL4;
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uint32_t TSEC_RND_CTL5;
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uint32_t TSEC_RND_CTL6;
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uint32_t TSEC_RND_CTL7;
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uint32_t TSEC_RND_CTL8;
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uint32_t TSEC_RND_CTL9;
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uint32_t TSEC_RND_CTL10;
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uint32_t TSEC_RND_CTL11;
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uint32_t _0x1530[0x34];
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uint32_t TSEC_TFBIF_CTL; /* Tegra Framebuffer Interface registers. */
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uint32_t TSEC_TFBIF_MCCIF_FIFOCTRL;
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uint32_t TSEC_TFBIF_THROTTLE;
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uint32_t TSEC_TFBIF_DBG_STAT0;
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uint32_t TSEC_TFBIF_DBG_STAT1;
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uint32_t TSEC_TFBIF_DBG_RDCOUNT_LO;
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uint32_t TSEC_TFBIF_DBG_RDCOUNT_HI;
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uint32_t TSEC_TFBIF_DBG_WRCOUNT_LO;
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uint32_t TSEC_TFBIF_DBG_WRCOUNT_HI;
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uint32_t TSEC_TFBIF_DBG_R32COUNT;
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uint32_t TSEC_TFBIF_DBG_R64COUNT;
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uint32_t TSEC_TFBIF_DBG_R128COUNT;
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uint32_t _0x1630;
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uint32_t TSEC_TFBIF_MCCIF_FIFOCTRL1;
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uint32_t TSEC_TFBIF_WRR_RDP;
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uint32_t _0x163C;
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uint32_t TSEC_TFBIF_SPROT_EMEM;
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uint32_t TSEC_TFBIF_TRANSCFG;
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uint32_t TSEC_TFBIF_REGIONCFG;
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uint32_t TSEC_TFBIF_ACTMON_ACTIVE_MASK;
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uint32_t TSEC_TFBIF_ACTMON_ACTIVE_BORPS;
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uint32_t TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT;
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uint32_t _0x1658[0x2];
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uint32_t TSEC_TFBIF_ACTMON_MCB_MASK;
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uint32_t TSEC_TFBIF_ACTMON_MCB_BORPS;
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uint32_t TSEC_TFBIF_ACTMON_MCB_WEIGHT;
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uint32_t _0x166C;
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uint32_t TSEC_TFBIF_THI_TRANSPROP;
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uint32_t _0x1674[0x17];
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uint32_t TSEC_CG; /* Clock Gate registers. */
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uint32_t _0x16D4[0xB];
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uint32_t TSEC_BAR0_CTL; /* HOST1X device DMA registers. */
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uint32_t TSEC_BAR0_ADDR;
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uint32_t TSEC_BAR0_DATA;
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uint32_t TSEC_BAR0_TIMEOUT;
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uint32_t _0x1710[0x3C];
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uint32_t TSEC_TEGRA_FALCON_IP_VER; /* Miscellaneous registers. */
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uint32_t _0x1804[0xD];
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uint32_t TSEC_TEGRA_CTL;
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uint32_t _0x183C[0x31];
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2018-08-18 17:59:33 +01:00
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} tegra_tsec_t;
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static inline volatile tegra_tsec_t *tsec_get_regs(void)
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{
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return (volatile tegra_tsec_t *)TSEC_BASE;
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}
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2018-11-29 23:32:31 +00:00
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void tsec_enable_clkrst();
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void tsec_disable_clkrst();
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2018-11-26 00:22:47 +00:00
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int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw_size);
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2018-11-29 23:32:31 +00:00
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int tsec_load_fw(const void *tsec_fw, size_t tsec_fw_size);
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void tsec_run_fw();
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2018-08-18 17:59:33 +01:00
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#endif
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