2018-05-04 18:47:05 +01:00
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#ifndef __APB_MISC_H__
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#define __APB_MISC_H__
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/* FIXME: clean up */
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#define MISC_BASE (0x70000000UL)
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#define PINMUX_BASE (MISC_BASE + 0x3000)
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#define PINMUX_AUX_GPIO_PZ1_0 (*(volatile uint32_t *)(PINMUX_BASE + 0x280))
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#define APB_MISC_GP_VGPIO_GPIO_MUX_SEL_0 MAKE_REG32(MISC_BASE + 0xb74)
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xa98)
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xab4)
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2018-06-05 18:07:14 +01:00
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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2018-05-04 18:47:05 +01:00
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#endif
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