2019-06-16 05:37:41 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _T210_H_
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#define _T210_H_
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#include "../utils/types.h"
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intptr_t QueryIoMapping(u64 addr, u64 size);
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define GPIO_BASE 0x6000D000
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#define GPIO_1_BASE (GPIO_BASE)
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#define GPIO_2_BASE (GPIO_BASE + 0x100)
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#define GPIO_3_BASE (GPIO_BASE + 0x200)
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#define GPIO_4_BASE (GPIO_BASE + 0x300)
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#define GPIO_5_BASE (GPIO_BASE + 0x400)
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#define GPIO_6_BASE (GPIO_BASE + 0x500)
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#define GPIO_7_BASE (GPIO_BASE + 0x600)
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define PWM_BASE 0x7000A000
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#define RTC_BASE 0x7000E000
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#define PMC_BASE 0x7000E400
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#define _REG(base, off) *(vu32 *)(QueryIoMapping((u64)base, 0) + (off))
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#define _REG_IO(base, off, size) *(vu32 *)(QueryIoMapping((u64)base, size) + (off))
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#define RTC(off) _REG_IO(RTC_BASE, off, 0x4000)
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#define TMR(off) _REG_IO(TMR_BASE, off, 0x3FF)
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#define CLOCK(off) _REG_IO(CLOCK_BASE, off, 0x1000)
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#define PMC(off) _REG_IO(PMC_BASE, off, 0x1000) // ??????????
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#define APB_MISC(off) _REG_IO(APB_MISC_BASE, off, 0x4000)
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#define PINMUX_AUX(off) _REG_IO(APB_MISC_BASE, off + (PINMUX_AUX_BASE - APB_MISC_BASE), 0x4000)
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#define GPIO(off) _REG_IO(GPIO_BASE, off, 0x1000)
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#define GPIO_1(off) _REG_IO(GPIO_BASE, off + (GPIO_1_BASE - GPIO_BASE), 0x1000)
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#define GPIO_2(off) _REG_IO(GPIO_BASE, off + (GPIO_2_BASE - GPIO_BASE), 0x1000)
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#define GPIO_3(off) _REG_IO(GPIO_BASE, off + (GPIO_3_BASE - GPIO_BASE), 0x1000)
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#define GPIO_4(off) _REG_IO(GPIO_BASE, off + (GPIO_4_BASE - GPIO_BASE), 0x1000)
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#define GPIO_5(off) _REG_IO(GPIO_BASE, off + (GPIO_5_BASE - GPIO_BASE), 0x1000)
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#define GPIO_6(off) _REG_IO(GPIO_BASE, off + (GPIO_6_BASE - GPIO_BASE), 0x1000)
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#define GPIO_7(off) _REG_IO(GPIO_BASE, off + (GPIO_7_BASE - GPIO_BASE), 0x1000)
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#define GPIO_8(off) _REG_IO(GPIO_BASE, off + (GPIO_8_BASE - GPIO_BASE), 0x1000)
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#define HOST1X(off) _REG(HOST1X_BASE, off)
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#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off)
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#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
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#define DSI(off) _REG(DSI_BASE, off)
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
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#define PWM(off) _REG(PWM_BASE, off)
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#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
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#define FUSE(off) _REG(FUSE_BASE, off)
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#define KFUSE(off) _REG(KFUSE_BASE, off)
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#define SE(off) _REG(SE_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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2020-06-09 00:26:55 +01:00
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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2019-06-16 05:37:41 +01:00
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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2020-06-09 00:26:55 +01:00
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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2019-06-16 05:37:41 +01:00
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
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/*! System registers. */
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_SPARE_REG 0x110
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/*! RTC registers. */
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#define APBDEV_RTC_SECONDS 0x8
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#define APBDEV_RTC_SHADOW_SECONDS 0xC
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#define APBDEV_RTC_MILLI_SECONDS 0x10
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/*! TMR registers. */
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) (TMR & 0xF)
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#define TIMER_PER(PER) ((PER & 0xFF) << 4)
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#define TIMER_SYSRESET_EN (1 << 14)
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#define TIMER_PMCRESET_EN (1 << 15)
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#define TIMER_WDT4_COMMAND (0x108 + 0x80)
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#define TIMER_START_CNT (1 << 0)
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#define TIMER_CNT_DISABLE (1 << 1)
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#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
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#define TIMER_MAGIC_PTRN 0xC45A
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#endif
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