2019-08-05 01:21:18 +01:00
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#include <string.h>
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2019-07-18 22:43:49 +01:00
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#include "utils.h"
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2019-07-29 21:38:44 +01:00
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#include "core_ctx.h"
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2019-07-31 01:30:17 +01:00
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#include "debug_log.h"
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2019-07-22 00:04:53 +01:00
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#include "platform/uart.h"
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2019-07-31 01:30:17 +01:00
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#include "semihosting.h"
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2019-07-30 01:16:25 +01:00
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#include "traps.h"
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2019-08-02 04:12:24 +01:00
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#include "sysreg.h"
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2019-08-05 01:21:18 +01:00
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#include "exceptions.h"
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#include "single_step.h"
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2019-08-05 22:49:25 +01:00
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#include "breakpoints.h"
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#include "watchpoints.h"
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2020-01-09 19:24:05 +00:00
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#include "timer.h"
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2019-08-10 23:56:49 +01:00
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#include "irq.h"
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2020-01-12 01:59:26 +00:00
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#include "transport_interface.h"
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2020-01-20 02:24:02 +00:00
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#include "guest_memory.h"
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2020-01-25 20:16:10 +00:00
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#include "fpu.h"
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2019-08-10 23:56:49 +01:00
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2020-01-17 22:10:26 +00:00
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#include "memory_map.h"
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#include "mmu.h"
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2019-07-31 01:30:17 +01:00
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static void loadKernelViaSemihosting(void)
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{
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2020-01-17 22:10:26 +00:00
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// Note: !! hardcoded addresses !!
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2019-07-31 01:30:17 +01:00
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size_t len = 1<<20; // max len
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2020-01-17 22:10:26 +00:00
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uintptr_t buf = 0x60000000 + (1<<20);
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2019-07-31 01:30:17 +01:00
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long handle = -1, ret;
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2020-01-17 22:10:26 +00:00
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u64 *mmuTable = (u64 *)MEMORY_MAP_VA_TTBL;
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mmu_map_block_range(
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1, mmuTable, 0x40000000, 0x40000000, 0x40000000,
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MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | MMU_PTE_BLOCK_MEMTYPE(MEMORY_MAP_MEMTYPE_NORMAL_UNCACHEABLE)
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);
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2020-01-20 02:24:02 +00:00
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__tlb_invalidate_el2_local();
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__dsb_local();
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2020-01-17 22:10:26 +00:00
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2019-07-31 23:46:16 +01:00
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DEBUG("Loading kernel via semihosted file I/O... ");
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2019-07-31 01:30:17 +01:00
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handle = semihosting_file_open("test_kernel.bin", FOPEN_MODE_RB);
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2020-01-25 17:20:43 +00:00
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ENSURE2(handle >= 0, "failed to open file (%ld)!\n", handle);
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2019-07-31 01:30:17 +01:00
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2020-01-25 17:20:43 +00:00
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ret = semihosting_file_read(handle, &len, buf);
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ENSURE2(ret >= 0, "failed to read file (%ld)!\n", ret);
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2019-07-31 01:30:17 +01:00
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2019-07-31 23:46:16 +01:00
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DEBUG("OK!\n");
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2019-07-31 01:30:17 +01:00
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semihosting_file_close(handle);
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2020-01-17 22:10:26 +00:00
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mmu_unmap_range(1, mmuTable, 0x40000000, 0x40000000);
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2020-01-20 02:24:02 +00:00
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__tlb_invalidate_el2_local();
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__dsb_local();
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2020-01-17 22:10:26 +00:00
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2019-07-31 01:30:17 +01:00
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currentCoreCtx->kernelEntrypoint = buf;
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}
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2020-01-12 21:51:50 +00:00
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#include "platform/uart.h"
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2020-01-27 00:46:00 +00:00
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#include "debug_manager.h"
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2020-01-12 21:51:50 +00:00
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typedef struct TestCtx {
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char buf[512+1];
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} TestCtx;
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static TestCtx g_testCtx;
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size_t testReceiveCallback(TransportInterface *iface, void *p)
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{
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TestCtx *ctx = (TestCtx *)p;
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2020-01-27 00:46:00 +00:00
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debugManagerPauseCores(BIT(0));
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2020-01-12 21:51:50 +00:00
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return transportInterfaceReadDataUntil(iface, ctx->buf, 512, '\r');
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}
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void testProcessDataCallback(TransportInterface *iface, void *p, size_t sz)
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{
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(void)iface;
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(void)sz;
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2020-01-30 01:22:37 +00:00
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debugManagerUnpauseCores(BIT(0));
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2020-01-12 21:51:50 +00:00
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TestCtx *ctx = (TestCtx *)p;
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DEBUG("EL2 [core %u]: you typed: %s\n", currentCoreCtx->coreId, ctx->buf);
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}
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void test(void)
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{
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TransportInterface *iface = transportInterfaceCreate(
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TRANSPORT_INTERFACE_TYPE_UART,
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DEFAULT_UART,
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DEFAULT_UART_FLAGS,
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testReceiveCallback,
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testProcessDataCallback,
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&g_testCtx
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);
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2020-01-14 02:09:51 +00:00
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transportInterfaceSetInterruptAffinity(iface, BIT(1));
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2020-01-12 21:51:50 +00:00
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}
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void thermosphereMain(ExceptionStackFrame *frame, u64 pct)
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2019-07-18 22:43:49 +01:00
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{
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2019-08-10 23:56:49 +01:00
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initIrq();
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2019-08-06 05:09:51 +01:00
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2019-08-07 20:38:40 +01:00
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if (currentCoreCtx->isBootCore) {
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2020-01-12 01:59:26 +00:00
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transportInterfaceInitLayer();
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debugLogInit();
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2020-01-31 23:23:41 +00:00
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//test();
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2020-01-31 02:53:40 +00:00
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debugManagerInit(TRANSPORT_INTERFACE_TYPE_UART, DEFAULT_UART, DEFAULT_UART_FLAGS);
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2019-08-07 20:38:40 +01:00
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DEBUG("EL2: core %u reached main first!\n", currentCoreCtx->coreId);
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}
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2020-01-12 01:59:26 +00:00
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enableTraps();
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enableBreakpointsAndWatchpoints();
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timerInit();
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2019-08-06 05:09:51 +01:00
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initBreakpoints();
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initWatchpoints();
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2019-07-30 01:16:25 +01:00
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2019-08-02 04:12:24 +01:00
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if (currentCoreCtx->isBootCore) {
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2019-07-31 01:30:17 +01:00
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if (currentCoreCtx->kernelEntrypoint == 0) {
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2020-01-25 17:20:43 +00:00
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ENSURE2(semihosting_connection_supported(), "Kernel not loaded!\n");
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loadKernelViaSemihosting();
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2019-07-31 01:30:17 +01:00
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}
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2019-07-29 21:38:44 +01:00
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}
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else {
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2019-07-31 23:46:16 +01:00
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DEBUG("EL2: core %u reached main!\n", currentCoreCtx->coreId);
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2019-07-29 21:38:44 +01:00
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}
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2019-07-19 00:45:56 +01:00
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2020-01-08 22:18:56 +00:00
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setCurrentCoreActive();
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2019-08-05 01:21:18 +01:00
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// Set up exception frame: init regs to 0, set spsr, elr, etc.
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memset(frame, 0, sizeof(ExceptionStackFrame));
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2020-01-08 22:18:56 +00:00
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frame->spsr_el2 = (0xF << 6) | (1 << 2) | 1; // EL1h+DAIF
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frame->elr_el2 = currentCoreCtx->kernelEntrypoint;
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frame->x[0] = currentCoreCtx->kernelArgument;
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2020-01-12 21:51:50 +00:00
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frame->cntpct_el0 = pct;
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2020-01-25 20:16:10 +00:00
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// Initialize FPU registers -- no need to memset, the regcaches are in .tempbss
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fpuCommitRegisters();
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fpuCleanInvalidateRegisterCache();
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2020-01-31 00:28:05 +00:00
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if (!currentCoreCtx->isBootCore) {
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debugManagerReportEvent(DBGEVENT_CORE_ON);
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2020-01-31 23:23:41 +00:00
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} else {
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debugManagerPauseCores(BIT(currentCoreCtx->coreId));
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2020-01-31 00:28:05 +00:00
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}
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2019-07-18 22:43:49 +01:00
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}
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