2019-02-20 14:31:46 +00:00
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/*
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2019-04-08 03:00:49 +01:00
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* Copyright (c) 2018-2019 Atmosphère-NX
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2019-02-20 14:31:46 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_APB_MISC_H
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#define FUSEE_APB_MISC_H
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#include <stdint.h>
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#define APB_MISC_BASE 0x70000000
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#define APB_PADCTL_BASE 0x70000810
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#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n)
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#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
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#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC2_ENABLE_DATA_IN (0xFF << 8)
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#define PADCTL_SDMMC2_ENABLE_CLK_IN (0x3 << 4)
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#define PADCTL_SDMMC2_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC4_ENABLE_DATA_IN (0xFF << 8)
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#define PADCTL_SDMMC4_ENABLE_CLK_IN (0x3 << 4)
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#define PADCTL_SDMMC4_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC1_CD_SOURCE (1 << 0)
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#define PADCTL_SDMMC1_WP_SOURCE (1 << 1)
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#define PADCTL_SDMMC3_CD_SOURCE (1 << 2)
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#define PADCTL_SDMMC3_WP_SOURCE (1 << 3)
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typedef struct {
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uint32_t asdbgreg; /* 0x810 */
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uint32_t reserved0[0x31];
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uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
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uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
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uint32_t emmc2_pad_cfg_control; /* 0x8DC */
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uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
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uint32_t _todo0[0x6E];
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uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
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uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
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uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
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uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
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uint32_t _todo1[0x03];
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uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
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uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
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uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
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uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
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uint32_t _todo2[0x2E];
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uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
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uint32_t qspi_sck_lpbk_control; /* 0xB78 */
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} tegra_padctl_t;
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static inline volatile tegra_padctl_t *padctl_get_regs(void)
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{
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return (volatile tegra_padctl_t *)APB_PADCTL_BASE;
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}
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#endif
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