2018-05-21 01:24:41 +01:00
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.macro GEN_USUAL_HANDLER name, index, lr_arm_displ, lr_thumb_displ
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_exception_handler_\name:
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ldr sp, =_regs
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stmia sp!, {r0-r7}
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/* Adjust lr to make it point to the location where the exception occured. */
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mrs r1, spsr
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tst r1, #0x20
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subeq lr, lr, #\lr_arm_displ
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subne lr, lr, #\lr_thumb_displ
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mov r0, sp
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mov r1, #\index
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b _exception_handler_common
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.endm
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.section .text.exception_handlers_asm, "ax", %progbits
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.arm
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.align 4
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_exception_handler_common:
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mrs r2, spsr
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mrs r3, cpsr
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/* Mask interrupts. */
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orr r3, #0xC0
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msr cpsr_cx, r3
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/* Switch to the mode that triggered the interrupt, get the remaining regs, switch back. */
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ands r4, r2, #0xF
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moveq r4, #0xF /* usr => sys */
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bic r5, r3, #0xF
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orr r5, r4
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msr cpsr_c, r5
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stmia r0!, {r8-lr}
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msr cpsr_c, r3
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str lr, [r0], #4
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str r2, [r0]
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/* Finally, switch to system mode, setting interrupts and clearing the flags; set sp as well. */
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msr cpsr_cxsf, #0xDF
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ldr sp, =(_exception_handler_stack + 0x1000)
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ldr r0, =_regs
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bl exception_handler_main
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b .
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GEN_USUAL_HANDLER undefined_instruction, 1, 4, 2
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GEN_USUAL_HANDLER swi, 2, 4, 2
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GEN_USUAL_HANDLER prefetch_abort, 3, 4, 4
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GEN_USUAL_HANDLER data_abort_normal, 4, 8, 8
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GEN_USUAL_HANDLER fiq, 7, 4, 4
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_exception_handler_data_abort:
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/* Mask interrupts (abort mode). */
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msr cpsr_cx, #0xD7
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2018-05-21 02:39:18 +01:00
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adr sp, safecpy+8
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2018-05-21 01:24:41 +01:00
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cmp lr, sp
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blo _exception_handler_data_abort_normal
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2018-05-21 02:39:18 +01:00
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adr sp, _safecpy_end+8
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2018-05-21 01:24:41 +01:00
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cmp lr, sp
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bhs _exception_handler_data_abort_normal
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/* Set the flags, set r12 to 0 for safecpy, return from exception. */
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msr spsr_f, #(1 << 30)
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mov r12, #0
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subs pc, lr, #4
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.global safecpy
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.type safecpy, %function
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safecpy:
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push {r4, lr}
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mov r3, #0
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movs r12, #1
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_safecpy_loop:
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ldrb r4, [r1, r3]
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cmp r12, #0
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beq _safecpy_loop_end
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strb r4, [r0, r3]
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add r3, #1
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cmp r3, r2
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blo _safecpy_loop
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_safecpy_loop_end:
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mov r0, r3
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2018-05-21 02:39:18 +01:00
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pop {r4, lr}
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bx lr /* Need to do that separately on ARMv4. */
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2018-05-21 01:24:41 +01:00
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_safecpy_end:
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.section .rodata.exception_handlers_asm, "a", %progbits
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.align 2
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.global exception_handler_table
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exception_handler_table:
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.word 0 /* Reset */
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.word _exception_handler_undefined_instruction
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.word _exception_handler_swi
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.word _exception_handler_prefetch_abort
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.word _exception_handler_data_abort
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.word 0 /* Reserved */
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.word 0 /* IRQ */
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.word _exception_handler_fiq
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.section .bss.exception_handlers_asm, "w", %nobits
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.align 4
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_exception_handler_stack: .skip 0x1000
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_regs: .skip (4 * 17)
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