2018-04-04 22:31:05 +01:00
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#ifndef FUSEE_SDMMC_H
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#define FUSEE_SDMMC_H
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#include <stdbool.h>
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#include <stdint.h>
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typedef struct {
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uint32_t SDHCI_DMA_ADDRESS;
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uint16_t SDHCI_BLOCK_SIZE;
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uint16_t SDHCI_BLOCK_COUNT;
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uint32_t SDHCI_ARGUMENT;
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uint16_t SDHCI_TRANSFER_MODE;
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uint16_t SDHCI_COMMAND;
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uint16_t SDHCI_RESPONSE[0x8];
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uint32_t SDHCI_BUFFER;
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uint32_t SDHCI_PRESENT_STATE;
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uint8_t SDHCI_HOST_CONTROL;
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uint8_t SDHCI_POWER_CONTROL;
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uint8_t SDHCI_BLOCK_GAP_CONTROL;
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uint8_t SDHCI_WAKE_UP_CONTROL;
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uint16_t SDHCI_CLOCK_CONTROL;
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uint8_t SDHCI_TIMEOUT_CONTROL;
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uint8_t SDHCI_SOFTWARE_RESET;
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uint32_t SDHCI_INT_STATUS;
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uint32_t SDHCI_INT_ENABLE;
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uint32_t SDHCI_SIGNAL_ENABLE;
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uint16_t SDHCI_ACMD12_ERR;
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uint16_t SDHCI_HOST_CONTROL2;
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uint32_t SDHCI_CAPABILITIES;
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uint32_t SDHCI_CAPABILITIES_1;
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uint32_t SDHCI_MAX_CURRENT;
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uint32_t _0x4C;
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uint16_t SDHCI_SET_ACMD12_ERROR;
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uint16_t SDHCI_SET_INT_ERROR;
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uint16_t SDHCI_ADMA_ERROR;
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uint8_t _0x55[0x3];
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uint32_t SDHCI_ADMA_ADDRESS;
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uint32_t SDHCI_UPPER_ADMA_ADDRESS;
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uint16_t SDHCI_PRESET_FOR_INIT;
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uint16_t SDHCI_PRESET_FOR_DEFAULT;
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uint16_t SDHCI_PRESET_FOR_HIGH;
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uint16_t SDHCI_PRESET_FOR_SDR12;
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uint16_t SDHCI_PRESET_FOR_SDR25;
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uint16_t SDHCI_PRESET_FOR_SDR50;
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uint16_t SDHCI_PRESET_FOR_SDR104;
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uint16_t SDHCI_PRESET_FOR_DDR50;
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uint8_t _0x70[0x3];
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uint32_t _0x74[0x22];
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uint16_t SDHCI_SLOT_INT_STATUS;
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uint16_t SDHCI_HOST_VERSION;
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} sdhci_registers_t;
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typedef struct {
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sdhci_registers_t standard_regs;
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uint32_t SDMMC_VENDOR_CLOCK_CNTRL;
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uint32_t SDMMC_VENDOR_SYS_SW_CNTRL;
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uint32_t SDMMC_VENDOR_ERR_INTR_STATUS;
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uint32_t SDMMC_VENDOR_CAP_OVERRIDES;
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uint32_t SDMMC_VENDOR_BOOT_CNTRL;
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uint32_t SDMMC_VENDOR_BOOT_ACK_TIMEOUT;
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uint32_t SDMMC_VENDOR_BOOT_DAT_TIMEOUT;
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uint32_t SDMMC_VENDOR_DEBOUNCE_COUNT;
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uint32_t SDMMC_VENDOR_MISC_CNTRL;
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uint32_t SDMMC_MAX_CURRENT_OVERRIDE;
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uint32_t SDMMC_MAX_CURRENT_OVERRIDE_HI;
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uint32_t _0x12C[0x21];
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uint32_t SDMMC_VENDOR_IO_TRIM_CNTRL;
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/* Start of SDMMC2/SDMMC4 only */
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uint32_t SDMMC_VENDOR_DLLCAL_CFG;
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uint32_t SDMMC_VENDOR_DLL_CTRL0;
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uint32_t SDMMC_VENDOR_DLL_CTRL1;
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uint32_t SDMMC_VENDOR_DLLCAL_CFG_STA;
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/* End of SDMMC2/SDMMC4 only */
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uint32_t SDMMC_VENDOR_TUNING_CNTRL0;
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uint32_t SDMMC_VENDOR_TUNING_CNTRL1;
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uint32_t SDMMC_VENDOR_TUNING_STATUS0;
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uint32_t SDMMC_VENDOR_TUNING_STATUS1;
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uint32_t SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT;
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uint32_t SDMMC_VENDOR_PRESET_VAL0;
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uint32_t SDMMC_VENDOR_PRESET_VAL1;
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uint32_t SDMMC_VENDOR_PRESET_VAL2;
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uint32_t SDMMC_SDMEMCOMPPADCTRL;
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uint32_t SDMMC_AUTO_CAL_CONFIG;
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uint32_t SDMMC_AUTO_CAL_INTERVAL;
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uint32_t SDMMC_AUTO_CAL_STATUS;
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uint32_t SDMMC_IO_SPARE;
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uint32_t SDMMC_SDMMCA_MCCIF_FIFOCTRL;
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uint32_t SDMMC_TIMEOUT_WCOAL_SDMMCA;
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uint32_t _0x1FC;
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} sdmmc_registers_t;
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc1_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0000);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc1b_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0000 + 0x1000);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc2_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0200);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc2b_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0200 + 0x2000);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc3_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0400);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc3b_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0400 + 0x3000);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc4_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0600);
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}
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2018-04-07 22:43:54 +01:00
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static inline volatile sdmmc_registers_t *get_sdmmc4b_regs(void) {
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2018-04-04 22:31:05 +01:00
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return (volatile sdmmc_registers_t *)(0x700B0600 + 0x4000);
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}
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#define SDMMC1_REGS (get_sdmmc1_regs())
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#define SDMMC2_REGS (get_sdmmc2_regs())
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#define SDMMC3_REGS (get_sdmmc3_regs())
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#define SDMMC4_REGS (get_sdmmc4_regs())
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void sdmmc1_init(void);
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void sdmmc2_init(void);
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void sdmmc3_init(void);
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void sdmmc4_init(void);
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#endif
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