2018-09-07 16:00:13 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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2020-01-24 10:10:40 +00:00
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* Copyright (c) 2018-2020 Atmosphère-NX
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2018-09-07 16:00:13 +01:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-08-18 17:59:33 +01:00
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#include "uart.h"
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#include "timers.h"
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2019-07-21 19:18:15 +01:00
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#include "pinmux.h"
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2019-07-23 23:37:24 +01:00
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static inline void uart_wait_cycles(uint32_t baud, uint32_t num)
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{
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udelay((num * 1000000 + 16 * baud - 1) / (16 * baud));
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}
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static inline void uart_wait_syms(uint32_t baud, uint32_t num)
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{
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udelay((num * 1000000 + baud - 1) / baud);
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}
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2019-07-21 19:18:15 +01:00
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void uart_config(UartDevice dev) {
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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2019-07-23 23:37:24 +01:00
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2019-07-21 19:18:15 +01:00
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switch (dev) {
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case UART_A:
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2019-07-21 21:21:13 +01:00
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pinmux->uart1_tx = 0;
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pinmux->uart1_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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2019-07-21 19:18:15 +01:00
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pinmux->uart1_rts = 0;
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pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_B:
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2019-07-21 21:21:13 +01:00
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pinmux->uart2_tx = 0;
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pinmux->uart2_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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2019-07-21 19:18:15 +01:00
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pinmux->uart2_rts = 0;
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pinmux->uart2_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_C:
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2019-07-21 21:21:13 +01:00
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pinmux->uart3_tx = 0;
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pinmux->uart3_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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2019-07-21 19:18:15 +01:00
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pinmux->uart3_rts = 0;
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pinmux->uart3_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_D:
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2019-07-21 21:21:13 +01:00
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pinmux->uart4_tx = 0;
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pinmux->uart4_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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2019-07-21 19:18:15 +01:00
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pinmux->uart4_rts = 0;
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pinmux->uart4_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_E:
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/* Unused. */
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break;
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default: break;
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}
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}
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2018-08-18 17:59:33 +01:00
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void uart_init(UartDevice dev, uint32_t baud) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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2019-07-21 19:18:15 +01:00
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/* Wait for idle state. */
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uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
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2019-07-23 23:37:24 +01:00
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/* Calculate baud rate, round to nearest. */
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2018-08-18 17:59:33 +01:00
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uint32_t rate = (8 * baud + 408000000) / (16 * baud);
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2019-07-21 19:18:15 +01:00
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/* Setup UART in FIFO mode. */
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2018-08-18 17:59:33 +01:00
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uart->UART_IER_DLAB = 0;
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uart->UART_MCR = 0;
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2019-07-21 19:18:15 +01:00
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uart->UART_LCR = (UART_LCR_DLAB | UART_LCR_WD_LENGTH_8); /* Enable DLAB and set word length 8. */
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uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
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uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
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uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */
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2019-07-23 23:37:24 +01:00
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uart->UART_SPR; /* Dummy read. */
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uart_wait_syms(baud, 3); /* Wait for 3 symbols at the new baudrate. */
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/* Enable FIFO with default settings. */
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uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO;
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uart->UART_SPR; /* Dummy read as mandated by TRM. */
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uart_wait_cycles(baud, 3); /* Wait for 3 baud cycles, as mandated by TRM (erratum). */
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2019-07-21 19:18:15 +01:00
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/* Flush FIFO. */
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2019-07-23 23:37:24 +01:00
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uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); /* Make sure there's no data being written in TX FIFO (TRM). */
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uart->UART_IIR_FCR |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Clear TX and RX FIFOs. */
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uart_wait_cycles(baud, 32); /* Wait for 32 baud cycles (TRM, erratum). */
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/* Wait for idle state (TRM). */
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2019-07-21 19:18:15 +01:00
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uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
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2018-08-18 17:59:33 +01:00
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}
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2019-07-21 19:18:15 +01:00
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/* This function blocks until the UART device is in the desired state. */
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2018-08-18 17:59:33 +01:00
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void uart_wait_idle(UartDevice dev, UartVendorStatus status) {
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2019-07-21 19:18:15 +01:00
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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if (status & UART_VENDOR_STATE_TX_IDLE) {
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while (!(uart->UART_LSR & UART_LSR_TMTY)) {
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/* Wait */
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}
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}
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if (status & UART_VENDOR_STATE_RX_IDLE) {
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while (uart->UART_LSR & UART_LSR_RDR) {
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/* Wait */
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}
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2018-08-18 17:59:33 +01:00
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}
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}
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void uart_send(UartDevice dev, const void *buf, size_t len) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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for (size_t i = 0; i < len; i++) {
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2019-07-21 19:18:15 +01:00
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while (!(uart->UART_LSR & UART_LSR_THRE)) {
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/* Wait until it's possible to send data. */
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2018-08-18 17:59:33 +01:00
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}
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uart->UART_THR_DLAB = *((const uint8_t *)buf + i);
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}
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}
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void uart_recv(UartDevice dev, void *buf, size_t len) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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for (size_t i = 0; i < len; i++) {
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2019-07-21 19:18:15 +01:00
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while (!(uart->UART_LSR & UART_LSR_RDR)) {
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/* Wait until it's possible to receive data. */
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2018-08-18 17:59:33 +01:00
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}
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*((uint8_t *)buf + i) = uart->UART_THR_DLAB;
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}
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}
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