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Code Issues Releases Activity

Set SDMMC controller to SDR104 as a workaround

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According to Tegra X1 Series Processors Silicon Errata there is possible
misalignment of received data which results in a CRC error. The issue is
present only in SDR50 mode.
This commit is contained in:
Tomasz Moń 2018-05-27 17:43:25 +02:00
parent c9723d7b68
commit 0534e36cf8
2 changed files with 4 additions and 2 deletions
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3
fusee/fusee-primary/src/sdmmc.c
View file

@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
case SDMMC_SPEED_SDR50:
mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
execute_tuning = true;
tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;

3
fusee/fusee-secondary/src/sdmmc.c
View file

@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
case SDMMC_SPEED_SDR50:
mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
execute_tuning = true;
tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;