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Set SDMMC controller to SDR104 as a workaround
According to Tegra X1 Series Processors Silicon Errata there is possible misalignment of received data which results in a CRC error. The issue is present only in SDR50 mode.
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2 changed files with 4 additions and 2 deletions
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@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
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case SDMMC_SPEED_SDR50:
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case SDMMC_SPEED_SDR50:
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mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
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mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
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mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
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mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
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sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
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// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
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sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
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execute_tuning = true;
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execute_tuning = true;
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tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;
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tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;
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@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
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case SDMMC_SPEED_SDR50:
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case SDMMC_SPEED_SDR50:
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mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
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mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
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mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
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mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
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sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
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// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
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sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
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execute_tuning = true;
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execute_tuning = true;
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tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;
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tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;
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