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KScheduler big brain strat for mdscr_el1 cfg change
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2 changed files with 7 additions and 12 deletions
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@ -62,8 +62,7 @@ namespace ams::kern {
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KThread *m_idle_thread;
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util::Atomic<KThread *> m_current_thread;
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public:
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constexpr KScheduler() : m_state(), m_is_active(false), m_core_id(0), m_last_context_switch_time(0), m_idle_thread(nullptr), m_current_thread(nullptr)
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{
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constexpr KScheduler() : m_state(), m_is_active(false), m_core_id(0), m_last_context_switch_time(0), m_idle_thread(nullptr), m_current_thread(nullptr) {
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m_state.needs_scheduling = true;
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m_state.interrupt_task_runnable = false;
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m_state.should_count_idle = false;
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@ -249,22 +249,18 @@ namespace ams::kern {
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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/* Ensure the single-step bit in mdscr reflects the correct single-step state for the new thread. */
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/* NOTE: Per ARM docs, changing the single-step bit requires a "context synchronization event" to */
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/* be sure that our new configuration takes. However, there are three types of synchronization event: */
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/* Taking an exception, returning from an exception, and ISB. The single-step bit change only matters */
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/* in EL0...which implies a return-from-exception has occurred since we set the bit. Thus, forcing */
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/* an ISB is unnecessary, and we can modify the register safely and be confident it will affect the next */
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/* userland instruction executed. */
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cpu::MonitorDebugSystemControlRegisterAccessor().SetSoftwareStep(next_thread->IsSingleStep()).Store();
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#endif
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/* Switch the current process, if we're switching processes. */
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if (KProcess *next_process = next_thread->GetOwnerProcess(); next_process != cur_process) {
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KProcess::Switch(cur_process, next_process);
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} else {
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/* The single-step bit set up above requires an instruction synchronization barrier, to ensure */
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/* the state change takes before we actually perform a return which might break-to-step. */
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/* KProcess::Switch performs an isb incidentally, and so when we're changing process we */
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/* can piggy-back off of that isb to avoid unnecessarily emptying the pipeline twice. */
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/* However, this means that when we're switching to thread in a different process, */
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/* we must ensure that we still isb. In practice, gcc will deduplicate into a single isb. */
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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cpu::InstructionMemoryBarrier();
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#endif
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}
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/* Set the new thread. */
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