Minor information update regarding previously unknown mysteries

exosphere/lp0fw/src/mc.h

@@ -35,6 +35,14 @@
 #define MC_SMMU_PTB_DATA                                        0x20
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
+#define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_PPCS1_ASID                                      0x298

exosphere/src/bootup.c

@@ -140,28 +140,26 @@ void bootup_misc_mmio(void) {
         APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
     }
 
-    /* Reset Translation Enable Registers. */
+    /* Reset Translation Enable registers. */
     MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_0) = 0xFFFFFFFF;
     MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_1) = 0xFFFFFFFF;
     MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_2) = 0xFFFFFFFF;
     MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_3) = 0xFFFFFFFF;
     MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF;
 
-    /* TODO: What are these MC reg writes? */
+    /* Set SMMU ASID security registers. */
     if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) {
-        MAKE_MC_REG(0x038) = 0xE;
+        MAKE_MC_REG(MC_SMMU_ASID_SECURITY) = 0xE;
     } else {
-        MAKE_MC_REG(0x038) = 0x0;
+        MAKE_MC_REG(MC_SMMU_ASID_SECURITY) = 0x0;
     }
-    MAKE_MC_REG(0x03C) = 0;
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_1) = 0;
-
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_2) = 0;
-    /* MISC registers. */
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_3) = 0;
-    MAKE_MC_REG(0x9E0) = 0;
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_4) = 0;
-    MAKE_MC_REG(0x9E4) = 0;
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_5) = 0;
-    MAKE_MC_REG(0x9E8) = 0;
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_6) = 0;
-    MAKE_MC_REG(0x9EC) = 0;
+    MAKE_MC_REG(MC_SMMU_ASID_SECURITY_7) = 0;
-    MAKE_MC_REG(0x9F0) = 0;
-    MAKE_MC_REG(0x9F4) = 0;
 
     if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) {
         MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0;

exosphere/src/mc.h

@@ -40,6 +40,14 @@ static inline uintptr_t get_mc_base(void) {
 #define MC_SMMU_PTB_DATA                                        0x20
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
+#define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_PPCS1_ASID                                      0x298

fusee/fusee-mtc/src/mc.h

@@ -37,6 +37,13 @@
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
 #define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_TSEC_ASID                                       0x294

fusee/fusee-primary/src/mc.h

@@ -37,6 +37,13 @@
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
 #define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_TSEC_ASID                                       0x294

fusee/fusee-secondary/src/mc.h

@@ -37,6 +37,13 @@
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
 #define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_TSEC_ASID                                       0x294

sept/sept-primary/src/mc.h

@@ -37,6 +37,13 @@
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
 #define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_TSEC_ASID                                       0x294

sept/sept-secondary/src/mc.h

@@ -37,6 +37,13 @@
 #define MC_SMMU_TLB_FLUSH                                       0x30
 #define MC_SMMU_PTC_FLUSH                                       0x34
 #define MC_SMMU_ASID_SECURITY                                   0x38
+#define MC_SMMU_ASID_SECURITY_1                                 0x3c
+#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
+#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
+#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
+#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
+#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
+#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
 #define MC_SMMU_AFI_ASID                                        0x238
 #define MC_SMMU_AVPC_ASID                                       0x23c
 #define MC_SMMU_TSEC_ASID                                       0x294

stratosphere/boot/source/boot_display.cpp

@@ -300,7 +300,12 @@ namespace sts::boot {
             for (size_t i = 0; i < util::size(host_response); i++) {
                 host_response[i] = reg::Read(g_dsi_regs + sizeof(u32) * DSI_RD_DATA);
             }
-
+            
+            /* The last word from host response is: 
+                Bits 0-7: FAB
+                Bits 8-15: REV
+                Bits 16-23: Minor REV
+            */
             if ((host_response[2] & 0xFF) == 0x10) {
                 g_lcd_vendor = 0;
             } else {
@@ -311,7 +316,7 @@ namespace sts::boot {
 
         /* LCD vendor specific configuration. */
         switch (g_lcd_vendor) {
-            case 0xF30: /* TODO: What's this? */
+            case 0xF30: /* AUO first revision screens. */
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
                 svcSleepThread(180'000'000ul);
@@ -327,7 +332,7 @@ namespace sts::boot {
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
                 break;
-            case 0xF20: /* TODO: What's this? */
+            case 0xF20: /* Innolux first revision screens. */
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
                 svcSleepThread(180'000'000ul);
@@ -347,6 +352,7 @@ namespace sts::boot {
                 DO_DSI_SLEEP_OR_REGISTER_WRITES(DisplayConfigJdiSpecificInit01);
                 break;
             default:
+                /* Innolux and AUO second revision screens. */
                 if ((g_lcd_vendor | 0x10) == 0x1030) {
                     reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
                     reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
@@ -445,11 +451,11 @@ namespace sts::boot {
             case 0x10:   /* Japan Display Inc screens. */
                 DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificFini01);
                 break;
-            case 0xF30:  /* TODO: What's this? */
+            case 0xF30:  /* AUO first revision screens. */
-                DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigF30SpecificFini01);
+                DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigAuoRev1SpecificFini01);
                 svcSleepThread(5'000'000ul);
                 break;
-            case 0x1020: /* TODO: What's this? */
+            case 0x1020: /* Innolux second revision screens. */
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
@@ -461,7 +467,7 @@ namespace sts::boot {
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
                 svcSleepThread(5'000'000ul);
                 break;
-            case 0x1030: /* TODO: What's this? */
+            case 0x1030: /* AUO second revision screens. */
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
                 reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);

stratosphere/boot/source/boot_display_config.inc

@@ -624,7 +624,7 @@ constexpr RegisterWrite DisplayConfigJdiSpecificFini01[] = {
     {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
 };
 
-constexpr RegisterWrite DisplayConfigF30SpecificFini01[] = {
+constexpr RegisterWrite DisplayConfigAuoRev1SpecificFini01[] = {
     {sizeof(u32) * DSI_WR_DATA, 0x439},
     {sizeof(u32) * DSI_WR_DATA, 0x9483FFB9},
     {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},