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kernel_ldr: bring initial cache flush in line with Nintendo

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This commit is contained in:
Michael Scire 2021-10-25 13:38:52 -07:00
parent 6ad3219656
commit 10ed579c38
1 changed files with 2 additions and 0 deletions
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libraries/libmesosphere/source/arch/arm64/kern_cpu.cpp
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@ -384,11 +384,13 @@ namespace ams::kern::arch::arm64::cpu {
/* Store cache from L1 up to (level of coherence - 1). */ /* Store cache from L1 up to (level of coherence - 1). */
for (int level = 0; level < levels_of_coherency - 1; ++level) { for (int level = 0; level < levels_of_coherency - 1; ++level) {
PerformCacheOperationBySetWayImpl<true>(level, StoreDataCacheLineBySetWayImpl); PerformCacheOperationBySetWayImpl<true>(level, StoreDataCacheLineBySetWayImpl);
DataSynchronizationBarrier();
} }
/* Flush cache from (level of coherence - 1) down to L0. */ /* Flush cache from (level of coherence - 1) down to L0. */
for (int level = levels_of_coherency; level > 0; --level) { for (int level = levels_of_coherency; level > 0; --level) {
PerformCacheOperationBySetWayImpl<true>(level - 1, FlushDataCacheLineBySetWayImpl); PerformCacheOperationBySetWayImpl<true>(level - 1, FlushDataCacheLineBySetWayImpl);
DataSynchronizationBarrier();
} }
} }