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kernel_ldr: bring initial cache flush in line with Nintendo
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@ -384,11 +384,13 @@ namespace ams::kern::arch::arm64::cpu {
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/* Store cache from L1 up to (level of coherence - 1). */
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for (int level = 0; level < levels_of_coherency - 1; ++level) {
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PerformCacheOperationBySetWayImpl<true>(level, StoreDataCacheLineBySetWayImpl);
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DataSynchronizationBarrier();
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}
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/* Flush cache from (level of coherence - 1) down to L0. */
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for (int level = levels_of_coherency; level > 0; --level) {
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PerformCacheOperationBySetWayImpl<true>(level - 1, FlushDataCacheLineBySetWayImpl);
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DataSynchronizationBarrier();
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}
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}
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