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thermosphere: also trap GICH (to deny access)

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This commit is contained in:
TuxSH 2019-08-14 15:48:07 +02:00
parent f9ec21e99e
commit 176be2386d
3 changed files with 12 additions and 6 deletions
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9
thermosphere/src/data_abort.c
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@ -46,6 +46,7 @@ void handleLowerElDataAbortException(ExceptionStackFrame *frame, ExceptionSyndro
memcpy(&dabtIss, &esr, 4); memcpy(&dabtIss, &esr, 4);
u64 far = GET_SYSREG(far_el2); u64 far = GET_SYSREG(far_el2);
u64 farpg = far & ~0xFFFull;
if (!dabtIss.isv || dabtIss.fnv) { if (!dabtIss.isv || dabtIss.fnv) {
dumpUnhandledDataAbort(dabtIss, far, ""); dumpUnhandledDataAbort(dabtIss, far, "");
@ -53,9 +54,11 @@ void handleLowerElDataAbortException(ExceptionStackFrame *frame, ExceptionSyndro
// TODO // TODO
if ((far & ~0xFFFull) == (uintptr_t)g_irqManager.gic.gicd) { if (farpg == (uintptr_t)g_irqManager.gic.gicd) {
// TODO // TODO
} } else if (farpg == (uintptr_t)g_irqManager.gic.gich) {
dumpUnhandledDataAbort(dabtIss, far, "GICH");
} else {
dumpUnhandledDataAbort(dabtIss, far, "(fallback)"); dumpUnhandledDataAbort(dabtIss, far, "(fallback)");
} }
}

5
thermosphere/src/platform/qemu/memory_map.c
View file

@ -72,8 +72,9 @@ uintptr_t configureStage2MemoryMap(u32 *addrSpaceSize)
identityMapL3(g_vttbl_l3_0, 0x08000000ull, BITL(21), unchanged); identityMapL3(g_vttbl_l3_0, 0x08000000ull, BITL(21), unchanged);
// GICD -> trapped, GICv2 CPU -> vCPU interface // GICD -> trapped, GICv2 CPU -> vCPU interface, GICH -> trapped (deny access)
mmu_unmap_range(3, g_vttbl_l3_0, 0x08000000, 0x10000ull); mmu_unmap_range(3, g_vttbl_l3_0, 0x08000000ull, 0x10000ull);
mmu_unmap_range(3, g_vttbl_l3_0, 0x08030000ull, 0x10000ull);
mmu_map_page_range(g_vttbl_l3_0, 0x08010000ull, 0x08040000ull, 0x10000ull, devattrs); mmu_map_page_range(g_vttbl_l3_0, 0x08010000ull, 0x08040000ull, 0x10000ull, devattrs);
} }

4
thermosphere/src/platform/tegra/memory_map.c
View file

@ -71,8 +71,10 @@ uintptr_t configureStage2MemoryMap(u32 *addrSpaceSize)
identityMapL3(g_vttbl_l3_0, 0x00000000ull, BITL(21), unchanged); identityMapL3(g_vttbl_l3_0, 0x00000000ull, BITL(21), unchanged);
// GICD -> trapped, GICv2 CPU -> vCPU interface // GICD -> trapped, GICv2 CPU -> vCPU interface, GICH -> trapped (access denied including for the unused view)
mmu_unmap_page(g_vttbl_l3_0, 0x50401000ull); mmu_unmap_page(g_vttbl_l3_0, 0x50401000ull);
mmu_unmap_page(g_vttbl_l3_0, 0x50404000ull);
mmu_unmap_page(g_vttbl_l3_0, 0x50405000ull);
mmu_map_page_range(g_vttbl_l3_0, 0x50042000ull, 0x50046000ull, 0x2000ull, devattrs); mmu_map_page_range(g_vttbl_l3_0, 0x50042000ull, 0x50046000ull, 0x2000ull, devattrs);
} }