mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-23 02:42:09 +00:00
kern: push code through call to kernelldr
This commit is contained in:
Michael Scire
parent
bce7133128
commit
24d41ce55e
2 changed files with 311 additions and 14 deletions
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@ -15,10 +15,10 @@ def main(argc, argv):
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kernel_ldr = f.read()
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with open('kernel/kernel.bin', 'rb') as f:
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kernel = f.read()
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kernel_metadata_offset = up('<I', kernel[4:8])[0]
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kernel_metadata_offset = 4
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assert (kernel_metadata_offset <= len(kernel) - 0x40)
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assert (kernel[kernel_metadata_offset:kernel_metadata_offset + 4] == b'MSS0')
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kernel_end = up('<I', kernel[kernel_metadata_offset + 0x30:kernel_metadata_offset + 0x34])[0]
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kernel_end = up('<I', kernel[kernel_metadata_offset + 0x34:kernel_metadata_offset + 0x38])[0]
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assert (kernel_end >= len(kernel))
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embedded_ini = b''
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@ -29,9 +29,9 @@ def main(argc, argv):
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kernel_ldr_end = kernel_ldr_offset + len(kernel_ldr)
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with open('mesosphere.bin', 'wb') as f:
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f.write(kernel[:kernel_metadata_offset + 8])
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f.write(pk('<II', embedded_ini_offset, kernel_ldr_offset))
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f.write(kernel[kernel_metadata_offset + 0x10:])
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f.write(kernel[:kernel_metadata_offset + 4])
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f.write(pk('<QQ', embedded_ini_offset, kernel_ldr_offset))
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f.write(kernel[kernel_metadata_offset + 0x14:])
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f.seek(embedded_ini_offset)
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f.write(embedded_ini)
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f.seek(embedded_ini_end)
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@ -18,18 +18,30 @@
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#define cpuactlr_el1 s3_1_c15_c2_0
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#define cpuectlr_el1 s3_1_c15_c2_1
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#define LOAD_IMMEDIATE_32(reg, val) \
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mov reg, #(((val) >> 0x00) & 0xFFFF); \
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl#16
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#define LOAD_IMMEDIATE_64(reg, val) \
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mov reg, #(((val) >> 0x00) & 0xFFFF); \
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl#16; \
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movk reg, #(((val) >> 0x20) & 0xFFFF), lsl#32; \
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movk reg, #(((val) >> 0x30) & 0xFFFF), lsl#48
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#define LOAD_FROM_LABEL(reg, label) \
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adr reg, label; \
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ldr reg, [reg]
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.section .crt0.text.start, "ax", %progbits
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.global _start
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_start:
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/* TODO */
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b _start
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.word (__metadata_begin - _start)
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b _ZN3ams4kern4init10StartCore0Emm
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__metadata_begin:
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.ascii "MSS0" /* Magic */
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.word 0 /* KInitArguments */
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.word 0 /* INI1 base address. */
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.word 0 /* Kernel Loader base address. */
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__metadata_ini_offset:
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.quad 0 /* INI1 base address. */
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__metadata_kernelldr_offset:
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.quad 0 /* Kernel Loader base address. */
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__metadata_kernel_layout:
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.word _start - _start /* rx_offset */
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.word __rodata_start - _start /* rx_end_offset */
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@ -43,6 +55,291 @@ __metadata_kernel_layout:
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.word _DYNAMIC - _start /* dynamic_offset */
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.word __init_array_start - _start /* init_array_offset */
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.word __init_array_end - _start /* init_array_end_offset */
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.if (. - __metadata_begin) != 0x40
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.if (. - __metadata_begin) != 0x44
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.error "Incorrect Mesosphere Metadata"
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.endif
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.endif
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/* ams::kern::init::StartCore0(uintptr_t, uintptr_t) */
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.section .crt0.text._ZN3ams4kern4init10StartCore0Emm, "ax", %progbits
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.global _ZN3ams4kern4init10StartCore0Emm
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.type _ZN3ams4kern4init10StartCore0Emm, %function
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_ZN3ams4kern4init10StartCore0Emm:
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/* Mask all interrupts. */
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msr daifset, #0xF
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/* Save arguments for later use. */
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mov x19, x0
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mov x20, x1
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/* Check our current EL. We want to be executing out of EL1. */
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/* If we're in EL2, we'll need to deprivilege ourselves. */
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mrs x1, currentel
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cmp x1, #0x4
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b.eq core0_el1
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cmp x1, #0x8
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b.eq core0_el2
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core0_el3:
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b core0_el3
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core0_el2:
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bl _ZN3ams4kern4init16JumpFromEL2ToEL1Ev
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core0_el1:
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bl _ZN3ams4kern4init19DisableMmuAndCachesEv
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/* We want to invoke kernel loader. */
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adr x0, _start
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adr x1, __metadata_kernel_layout
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LOAD_FROM_LABEL(x2, __metadata_ini_offset)
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add x2, x0, x2
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LOAD_FROM_LABEL(x3, __metadata_kernelldr_offset)
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add x3, x0, x3
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blr x3
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/* TODO: Finish post-kernelldr init code. */
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1:
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b 1b
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/* ams::kern::init::JumpFromEL2ToEL1() */
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.section .crt0.text._ZN3ams4kern4init16JumpFromEL2ToEL1Ev, "ax", %progbits
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.global _ZN3ams4kern4init16JumpFromEL2ToEL1Ev
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.type _ZN3ams4kern4init16JumpFromEL2ToEL1Ev, %function
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_ZN3ams4kern4init16JumpFromEL2ToEL1Ev:
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/* We're going to want to ERET to our caller. */
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msr elr_el2, x30
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/* Ensure that the cache is coherent. */
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bl _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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bl _ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv
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dsb sy
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bl _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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/* Invalidate the entire TLB, and ensure instruction consistency. */
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tlbi vmalle1is
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dsb sy
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isb
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/* Setup system registers for deprivileging. */
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/* ACTLR_EL2: */
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/* - CPUACTLR access control = 1 */
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/* - CPUECTLR access control = 1 */
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/* - L2CTLR access control = 1 */
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/* - L2ECTLR access control = 1 */
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/* - L2ACTLR access control = 1 */
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mov x0, #0x73
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msr actlr_el2, x0
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/* HCR_EL2: */
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/* - RW = 1 (el1 is aarch64) */
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mov x0, #0x80000000
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msr hcr_el2, x0
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/* SCTLR_EL1: */
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/* - EOS = 1 */
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/* - EIS = 1 */
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/* - SPAN = 1 */
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LOAD_IMMEDIATE_32(x0, 0x00C00800)
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msr sctlr_el1, x0
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/* DACR32_EL2: */
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/* - Manager access for all D<n> */
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mov x0, #0xFFFFFFFF
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msr dacr32_el2, x0
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/* SPSR_EL2: */
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/* - EL1h */
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/* - IRQ masked */
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/* - FIQ masked */
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mov x0, #0xC5
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msr spsr_el2, x0
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eret
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/* ams::kern::init::DisableMmuAndCaches() */
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.section .crt0.text._ZN3ams4kern4init19DisableMmuAndCachesEv, "ax", %progbits
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.global _ZN3ams4kern4init19DisableMmuAndCachesEv
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.type _ZN3ams4kern4init19DisableMmuAndCachesEv, %function
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_ZN3ams4kern4init19DisableMmuAndCachesEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x22, x30
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/* Ensure that the cache is coherent. */
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bl _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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bl _ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv
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dsb sy
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bl _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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dsb sy
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/* Invalidate the entire TLB, and ensure instruction consistency. */
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tlbi vmalle1is
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dsb sy
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isb
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/* Invalidate the instruction cache, and ensure instruction consistency. */
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ic ialluis
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dsb sy
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isb
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/* Set SCTLR_EL1 to disable the caches and mmu. */
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/* SCTLR_EL1: */
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/* - M = 0 */
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/* - C = 0 */
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/* - I = 0 */
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mrs x0, sctlr_el1
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LOAD_IMMEDIATE_64(x1, ~0x1005)
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and x0, x0, x1
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msr sctlr_el1, x0
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mov x30, x22
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ret
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/* ams::kern::arm64::cpu::FlushEntireDataCacheLocalWithoutStack() */
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.section .crt0.text._ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv
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.type _ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv, %function
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_ZN3ams4kern5arm643cpu37FlushEntireDataCacheLocalWithoutStackEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x23, x30
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/* CacheLineIdAccessor clidr_el1; */
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mrs x10, clidr_el1
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/* const int levels_of_unification = clidr_el1.GetLevelsOfUnification(); */
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ubfx x10, x10, #0x15, 3
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/* int level = levels_of_unification - 1 */
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sub w9, w10, #1
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/* while (level >= 0) { */
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begin_flush_cache_local_loop:
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cmn w9, #1
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b.eq done_flush_cache_local_loop
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/* FlushEntireDataCacheImplWithoutStack(level); */
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mov w0, w9
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bl _ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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/* level--; */
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sub w9, w9, #1
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/* } */
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b begin_flush_cache_local_loop
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done_flush_cache_local_loop:
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mov x30, x23
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ret
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/* ams::kern::arm64::cpu::FlushEntireDataCacheSharedWithoutStack() */
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.section .crt0.text._ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv
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.type _ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv, %function
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_ZN3ams4kern5arm643cpu38FlushEntireDataCacheSharedWithoutStackEv:
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/* The stack isn't set up, so we'll need to trash a register. */
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mov x23, x30
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/* CacheLineIdAccessor clidr_el1; */
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mrs x10, clidr_el1
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/* const int levels_of_coherency = clidr_el1.GetLevelsOfCoherency(); */
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ubfx x9, x10, #0x18, 3
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/* const int levels_of_unification = clidr_el1.GetLevelsOfUnification(); */
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ubfx x10, x10, #0x15, 3
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/* int level = levels_of_coherency */
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/* while (level >= levels_of_unification) { */
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begin_flush_cache_shared_loop:
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cmp w10, w9
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b.gt done_flush_cache_shared_loop
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/* FlushEntireDataCacheImplWithoutStack(level); */
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mov w0, w9
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bl _ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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/* level--; */
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sub w9, w9, #1
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/* } */
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b begin_flush_cache_shared_loop
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done_flush_cache_shared_loop:
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mov x30, x23
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ret
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/* ams::kern::arm64::cpu::FlushEntireDataCacheImplWithoutStack() */
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.section .crt0.text._ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv, "ax", %progbits
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.global _ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv
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.type _ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv, %function
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_ZN3ams4kern5arm643cpu36FlushEntireDataCacheImplWithoutStackEv:
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/* const u64 level_sel_value = static_cast<u64>(level << 1); */
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lsl w6, w0, #1
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sxtw x6, w6
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/* cpu::SetCsselrEl1(level_sel_value); */
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msr csselr_el1, x6
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/* cpu::InstructionMemoryBarrier(); */
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isb
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/* CacheSizeIdAccessor ccsidr_el1; */
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mrs x3, ccsidr_el1
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/* const int num_ways = ccsidr_el1.GetAssociativity(); */
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ubfx x7, x3, #3, #0xA
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mov w8, w7
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/* const int line_size = ccsidr_el1.GetLineSize(); */
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and x4, x3, #7
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/* const u64 way_shift = static_cast<u64>(__builtin_clz(num_ways)); */
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clz w7, w7
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/* const u64 set_shift = static_cast<u64>(line_size + 4); */
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add w4, w4, #4
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/* const int num_sets = ccsidr_el1.GetNumberOfSets(); */
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ubfx w3, w3, #0xD, #0xF
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/* int way = 0; */
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mov x5, #0
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/* while (way <= num_ways) { */
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begin_flush_cache_impl_way_loop:
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cmp w8, w5
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b.lt done_flush_cache_impl_way_loop
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/* int set = 0; */
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mov x0, #0
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/* while (set <= num_sets) { */
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begin_flush_cache_impl_set_loop:
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cmp w3, w0
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b.lt done_flush_cache_impl_set_loop
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/* const u64 cisw_value = (static_cast<u64>(way) << way_shift) | (static_cast<u64>(set) << set_shift) | level_sel_value; */
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lsl x2, x5, x7
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lsl x1, x0, x4
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orr x1, x1, x2
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orr x1, x1, x6
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/* __asm__ __volatile__("dc cisw, %0" :: "r"(cisw_value) : "memory"); */
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dc cisw, x1
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/* set++; */
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add x0, x0, #1
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/* } */
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b begin_flush_cache_impl_set_loop
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done_flush_cache_impl_set_loop:
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/* way++; */
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add x5, x5, 1
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/* } */
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b begin_flush_cache_impl_way_loop
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done_flush_cache_impl_way_loop:
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ret
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