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kern: assume that uart has been setup by secmon

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Michael Scire 2020-12-01 17:30:42 -08:00 committed by SciresM
parent 7e1da15f6e
commit 2b483866c7
2 changed files with 13 additions and 28 deletions
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2
libraries/libmesosphere/include/mesosphere/kern_k_thread.hpp
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@ -341,7 +341,7 @@ namespace ams::kern {
constexpr KThreadContext &GetContext() { return this->thread_context; } constexpr KThreadContext &GetContext() { return this->thread_context; }
constexpr const KThreadContext &GetContext() const { return this->thread_context; } constexpr const KThreadContext &GetContext() const { return this->thread_context; }
constexpr const u64 GetVirtualAffinityMask() const { return this->virtual_affinity_mask; } constexpr u64 GetVirtualAffinityMask() const { return this->virtual_affinity_mask; }
constexpr const KAffinityMask &GetAffinityMask() const { return this->physical_affinity_mask; } constexpr const KAffinityMask &GetAffinityMask() const { return this->physical_affinity_mask; }
Result GetCoreMask(int32_t *out_ideal_core, u64 *out_affinity_mask); Result GetCoreMask(int32_t *out_ideal_core, u64 *out_affinity_mask);

39
libraries/libmesosphere/source/kern_debug_log_impl.board.nintendo_nx.cpp
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@ -51,37 +51,22 @@ namespace ams::kern {
} }
bool KDebugLogImpl::Initialize() { bool KDebugLogImpl::Initialize() {
/* Get the uart memory region. */
const KMemoryRegion *uart_region = KMemoryLayout::GetPhysicalMemoryRegionTree().FindFirstDerived(KMemoryRegionType_Uart);
if (uart_region == nullptr) {
return false;
}
/* Set the uart register base address. */ /* Set the uart register base address. */
g_uart_address = KMemoryLayout::GetDeviceVirtualAddress(KMemoryRegionType_Uart); g_uart_address = uart_region->GetPairAddress();
if (g_uart_address == Null<KVirtualAddress>) {
return false;
}
/* Parameters for uart. */ /* NOTE: We assume here that UART init/config has been done by the Secure Monitor. */
constexpr u32 BaudRate = 115200; /* As such, we only need to disable interrupts. */
constexpr u32 Pllp = 408000000;
constexpr u32 Rate = 16 * BaudRate;
constexpr u32 Divisor = (Pllp + Rate / 2) / Rate;
/* Initialize the UART registers. */
/* Set Divisor Latch Access bit, to allow access to DLL/DLH */
WriteUartRegister(UartRegister_LCR, 0x80);
ReadUartRegister(UartRegister_LCR);
/* Program the divisor into DLL/DLH. */
WriteUartRegister(UartRegister_DLL, Divisor & 0xFF);
WriteUartRegister(UartRegister_DLH, (Divisor >> 8) & 0xFF);
ReadUartRegister(UartRegister_DLH);
/* Set word length to 3, clear Divisor Latch Access. */
WriteUartRegister(UartRegister_LCR, 0x03);
ReadUartRegister(UartRegister_LCR);
/* Disable UART interrupts. */
WriteUartRegister(UartRegister_IER, 0x00); WriteUartRegister(UartRegister_IER, 0x00);
/* Configure the FIFO to be enabled and clear receive. */
WriteUartRegister(UartRegister_FCR, 0x03);
WriteUartRegister(UartRegister_IRDA_CSR, 0x02);
ReadUartRegister(UartRegister_FCR);
return true; return true;
} }