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Code Issues Releases Activity

exo: fix data abort in car access

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This commit is contained in:
Michael Scire 2019-12-31 13:48:35 -08:00
parent 5fbd728962
commit 2e8f06ef44
2 changed files with 20 additions and 20 deletions
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32
exosphere/lp0fw/src/car.c
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@ -13,7 +13,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <stdint.h> #include <stdint.h>
#include "utils.h" #include "utils.h"
@ -33,7 +33,7 @@ static inline uint32_t get_special_clk_reg(CarDevice dev) {
case CARDEVICE_BPMP: return 0; case CARDEVICE_BPMP: return 0;
default: reboot(); default: reboot();
} }
} }
static inline uint32_t get_special_clk_val(CarDevice dev) { static inline uint32_t get_special_clk_val(CarDevice dev) {
switch (dev) { switch (dev) {
@ -48,19 +48,19 @@ static inline uint32_t get_special_clk_val(CarDevice dev) {
} }
static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4};
static uint32_t g_clk_clr_reg_offsets[NUM_CAR_BANKS] = {0x324, 0x32C, 0x334, 0x444, 0x44C, 0x228, 0x2A0}; static uint32_t g_clk_clr_reg_offsets[NUM_CAR_BANKS] = {0x324, 0x32C, 0x334, 0x444, 0x44C, 0x228, 0x2A0};
void car_configure_oscillators(void) { void car_configure_oscillators(void) {
/* Enable the crystal oscillator, setting drive strength to the saved value in PMC. */ /* Enable the crystal oscillator, setting drive strength to the saved value in PMC. */
CLK_RST_CONTROLLER_OSC_CTRL_0 = (CLK_RST_CONTROLLER_OSC_CTRL_0 & 0xFFFFFC0E) | 1 | (((APBDEV_PMC_OSC_EDPD_OVER_0 >> 1) & 0x3F) << 4); CLK_RST_CONTROLLER_OSC_CTRL_0 = (CLK_RST_CONTROLLER_OSC_CTRL_0 & 0xFFFFFC0E) | 1 | (((APBDEV_PMC_OSC_EDPD_OVER_0 >> 1) & 0x3F) << 4);
/* Set CLK_M_DIVISOR to 1 (causes actual division by 2.) */ /* Set CLK_M_DIVISOR to 1 (causes actual division by 2.) */
CLK_RST_CONTROLLER_SPARE_REG0_0 = (1 << 2); CLK_RST_CONTROLLER_SPARE_REG0_0 = (1 << 2);
/* Reading the register after writing it is required to ensure value takes. */ /* Reading the register after writing it is required to ensure value takes. */
(void)(CLK_RST_CONTROLLER_SPARE_REG0_0); (void)(CLK_RST_CONTROLLER_SPARE_REG0_0);
/* Set TIMERUS_USEC_CFG to cycle at 0x60 / 0x5 = 19.2 MHz. */ /* Set TIMERUS_USEC_CFG to cycle at 0x60 / 0x5 = 19.2 MHz. */
/* Value is (dividend << 8) | (divisor). */ /* Value is (dividend << 8) | (divisor). */
TIMERUS_USEC_CFG_0 = 0x45F; TIMERUS_USEC_CFG_0 = 0x45F;
@ -68,30 +68,30 @@ void car_configure_oscillators(void) {
void car_mbist_workaround(void) { void car_mbist_workaround(void) {
/* This code works around MBIST bug. */ /* This code works around MBIST bug. */
/* Clear LVL2_CLK_GATE_OVR* registers. */ /* Clear LVL2_CLK_GATE_OVR* registers. */
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0 = 0; CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0 = 0;
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0 = 0; CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0 = 0;
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0 = 0; CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0 = 0;
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 = 0; CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 = 0;
CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0 = 0; CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0 = 0;
/* Clear bit patterns in CAR. */ /* Clear bit patterns in CAR. */
/* L: Reset all but RTC, TMR, GPIO, BPMP Cache (CACHE2). */ /* L: Reset all but RTC, TMR, GPIO, BPMP Cache (CACHE2). */
MAKE_CAR_REG(g_clk_clr_reg_offsets[0]) = MAKE_CAR_REG(g_clk_reg_offsets[0]) & 0x7FFFFECF; MAKE_CAR_REG(g_clk_clr_reg_offsets[0]) = MAKE_CAR_REG(g_clk_reg_offsets[0]) & 0x7FFFFECF;
/* H: Reset all but MC, PMC, FUSE, EMC. */ /* H: Reset all but MC, PMC, FUSE, EMC. */
MAKE_CAR_REG(g_clk_clr_reg_offsets[1]) = MAKE_CAR_REG(g_clk_reg_offsets[1]) & 0xFDFFFF3E; MAKE_CAR_REG(g_clk_clr_reg_offsets[1]) = MAKE_CAR_REG(g_clk_reg_offsets[1]) & 0xFDFFFF3E;
/* U: Reset all but CSITE, IRAM[A-D], BPMP Cache RAM (CRAM2). */ /* U: Reset all but CSITE, IRAM[A-D], BPMP Cache RAM (CRAM2). */
MAKE_CAR_REG(g_clk_clr_reg_offsets[2]) = MAKE_CAR_REG(g_clk_reg_offsets[2]) & 0xFE0FFDFF; MAKE_CAR_REG(g_clk_clr_reg_offsets[2]) = MAKE_CAR_REG(g_clk_reg_offsets[2]) & 0xFE0FFDFF;
/* V: Reset all but MSELECT, S/PDIF audio doubler, TZRAM, SE. */ /* V: Reset all but MSELECT, S/PDIF audio doubler, TZRAM, SE. */
MAKE_CAR_REG(g_clk_clr_reg_offsets[3]) = MAKE_CAR_REG(g_clk_reg_offsets[3]) & 0x3FBFFFF7; MAKE_CAR_REG(g_clk_clr_reg_offsets[3]) = MAKE_CAR_REG(g_clk_reg_offsets[3]) & 0x3FBFFFF7;
/* W: Reset all but PCIERX[0-5], ENTROPY. */ /* W: Reset all but PCIERX[0-5], ENTROPY. */
MAKE_CAR_REG(g_clk_clr_reg_offsets[4]) = MAKE_CAR_REG(g_clk_reg_offsets[4]) & 0xFFDFFF03; MAKE_CAR_REG(g_clk_clr_reg_offsets[4]) = MAKE_CAR_REG(g_clk_reg_offsets[4]) & 0xFFDFFF03;
/* X: Reset all but ETC, MCLK, MCLK2, I2C6, EMC_DLL, GPU, DBGAPB, PLLG_REF, . */ /* X: Reset all but ETC, MCLK, MCLK2, I2C6, EMC_DLL, GPU, DBGAPB, PLLG_REF, . */
MAKE_CAR_REG(g_clk_clr_reg_offsets[5]) = MAKE_CAR_REG(g_clk_reg_offsets[5]) & 0xDCFFB87F; MAKE_CAR_REG(g_clk_clr_reg_offsets[5]) = MAKE_CAR_REG(g_clk_reg_offsets[5]) & 0xDCFFB87F;
/* Y: Reset all but MC_CDPA, MC_CCPA. */ /* Y: Reset all but MC_CDPA, MC_CCPA. */
MAKE_CAR_REG(g_clk_clr_reg_offsets[6]) = MAKE_CAR_REG(g_clk_reg_offsets[6]) & 0xFFFFFCFF; MAKE_CAR_REG(g_clk_clr_reg_offsets[6]) = MAKE_CAR_REG(g_clk_reg_offsets[6]) & 0xFFFFFCFF;
/* Enable clock to MC1, if CH1 is enabled in EMC. */ /* Enable clock to MC1, if CH1 is enabled in EMC. */
if (EMC_FBIO_CFG7_0 & 4) { /* CH1_ENABLE */ if (EMC_FBIO_CFG7_0 & 4) { /* CH1_ENABLE */
CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 |= 0x40000000; /* SET_CLK_ENB_MC1 */ CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 |= 0x40000000; /* SET_CLK_ENB_MC1 */
@ -134,5 +134,5 @@ void clkrst_reboot(CarDevice dev) {
} }
void clkrst_enable_fuse_regs(bool enable) { void clkrst_enable_fuse_regs(bool enable) {
MAKE_CAR_REG(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) = ((MAKE_CAR_REG(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) & 0xEFFFFFFF) | ((enable & 1) << 28)); CLK_RST_CONTROLLER_MISC_CLK_ENB_0 = ((CLK_RST_CONTROLLER_MISC_CLK_ENB_0 & 0xEFFFFFFF) | ((enable & 1) << 28));
} }

8
exosphere/src/car.c
View file

@ -13,7 +13,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <stdint.h> #include <stdint.h>
#include "utils.h" #include "utils.h"
@ -30,7 +30,7 @@ static inline uint32_t get_special_clk_reg(CarDevice dev) {
case CARDEVICE_BPMP: return 0; case CARDEVICE_BPMP: return 0;
default: generic_panic(); default: generic_panic();
} }
} }
static inline uint32_t get_special_clk_val(CarDevice dev) { static inline uint32_t get_special_clk_val(CarDevice dev) {
switch (dev) { switch (dev) {
@ -45,7 +45,7 @@ static inline uint32_t get_special_clk_val(CarDevice dev) {
} }
static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4};
void clk_enable(CarDevice dev) { void clk_enable(CarDevice dev) {
uint32_t special_reg; uint32_t special_reg;
@ -83,5 +83,5 @@ void clkrst_reboot(CarDevice dev) {
} }
void clkrst_enable_fuse_regs(bool enable) { void clkrst_enable_fuse_regs(bool enable) {
MAKE_CAR_REG(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) = ((MAKE_CAR_REG(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) & 0xEFFFFFFF) | ((enable & 1) << 28)); CLK_RST_CONTROLLER_MISC_CLK_ENB_0 = ((CLK_RST_CONTROLLER_MISC_CLK_ENB_0 & 0xEFFFFFFF) | ((enable & 1) << 28));
} }