mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-22 11:56:40 +00:00
fusee: Minor bugfixes.
This commit is contained in:
parent
ad4605abde
commit
2f8edfa8e2
14 changed files with 40 additions and 52 deletions
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@ -70,7 +70,7 @@ void display_init()
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/* Enable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
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udelay(10000u);
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udelay(10000);
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/* Enable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
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@ -165,12 +165,7 @@ void display_end()
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
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MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
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uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5;
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while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) {
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/* Wait. */
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}
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5;
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
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exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17);
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@ -182,7 +177,7 @@ void display_end()
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exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22);
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MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
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MAKE_DSI_REG(DSI_TRIGGER) = 2;
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MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
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udelay(50000);
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@ -207,7 +202,7 @@ void display_end()
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car->rst_dev_l_set = 0x18000000;
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car->clk_enb_l_clr = 0x18000000;
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MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F;
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MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
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MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
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/* Backlight PWM. */
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@ -236,17 +231,16 @@ void display_color_screen(uint32_t color)
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uint32_t *display_init_framebuffer(void *address)
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{
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static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0};
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if(conf[0].val == 0) {
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if (conf[0].val == 0) {
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for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) {
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conf[i] = cfg_display_framebuffer[i];
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}
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}
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uint32_t *lfb_addr = (uint32_t *)address;
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conf[19].val = (uint32_t)address;
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//This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768).
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/* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
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exec_cfg((uint32_t *)DI_BASE, conf, 32);
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udelay(35000);
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@ -4,7 +4,7 @@
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#include <stdint.h>
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#define FLOW_CTLR_BASE 0x60007000
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#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs)
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#define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n)
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#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
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#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040)
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@ -24,7 +24,7 @@ void config_oscillators()
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car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
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SYSCTR0_CNTFID0_0 = 19200000;
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MAKE_TIMERS_REG(0x14) = 0x45F;
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TIMERUS_USEC_CFG_0 = 0x45F;
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car->osc_ctrl = 0x50000071;
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pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
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@ -60,7 +60,7 @@ int max77620_regulator_get_status(uint32_t id)
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}
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if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
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return (val & 8) ? 0 : 1;
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return (val & 8) ? 1 : 0;
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return 0;
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}
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@ -20,7 +20,7 @@ void mc_config_carveout()
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MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
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MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
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mc_config_tsec_carveout(0, 0, 1);
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mc_config_tsec_carveout(0, 0, true);
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MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
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MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
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@ -5,13 +5,14 @@
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#define TIMERS_BASE 0x60005000
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#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
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#define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10)
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#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
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#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
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#define RTC_BASE 0x7000E000
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#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
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#define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08)
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#define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C)
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#define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10)
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#define RTC_SECONDS MAKE_RTC_REG(0x08)
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#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
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#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
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typedef struct {
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uint32_t CONFIG;
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@ -22,7 +23,7 @@ typedef struct {
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#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
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#define WDT_REBOOT_PATTERN 0xC45A
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#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8*n)
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#define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
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void wait(uint32_t microseconds);
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@ -110,7 +110,7 @@ void cluster_boot_cpu0(uint32_t entry)
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/* Request and wait for RAM repair. */
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FLOW_CTLR_RAM_REPAIR_0 = 1;
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while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)){
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while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)) {
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/* Wait. */
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}
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@ -70,7 +70,7 @@ void display_init()
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/* Enable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
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udelay(10000u);
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udelay(10000);
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/* Enable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
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@ -165,12 +165,7 @@ void display_end()
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
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MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
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uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5;
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while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) {
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/* Wait. */
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}
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5;
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
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exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17);
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@ -182,7 +177,7 @@ void display_end()
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exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22);
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MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
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MAKE_DSI_REG(DSI_TRIGGER) = 2;
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MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
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udelay(50000);
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@ -207,7 +202,7 @@ void display_end()
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car->rst_dev_l_set = 0x18000000;
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car->clk_enb_l_clr = 0x18000000;
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MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F;
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MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
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MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
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/* Backlight PWM. */
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@ -236,17 +231,16 @@ void display_color_screen(uint32_t color)
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uint32_t *display_init_framebuffer(void *address)
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{
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static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0};
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if(conf[0].val == 0) {
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if (conf[0].val == 0) {
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for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) {
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conf[i] = cfg_display_framebuffer[i];
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}
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}
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uint32_t *lfb_addr = (uint32_t *)address;
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conf[19].val = (uint32_t)address;
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//This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768).
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/* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
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exec_cfg((uint32_t *)DI_BASE, conf, 32);
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udelay(35000);
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@ -4,7 +4,7 @@
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#include <stdint.h>
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#define FLOW_CTLR_BASE 0x60007000
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#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs)
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#define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n)
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#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
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#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040)
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@ -60,7 +60,7 @@ int max77620_regulator_get_status(uint32_t id)
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}
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if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
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return (val & 8) ? 0 : 1;
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return (val & 8) ? 1 : 0;
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return 0;
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}
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@ -20,7 +20,7 @@ void mc_config_carveout()
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MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
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MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
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mc_config_tsec_carveout(0, 0, 1);
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mc_config_tsec_carveout(0, 0, true);
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MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
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MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
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@ -133,7 +133,7 @@ static void nxboot_set_bootreason() {
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boot_reason.boot_reason_state = 0x04;
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/* Set in memory. */
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memcpy((void *)MAILBOX_NX_BOOTLOADER_BOOT_REASON, &boot_reason, sizeof(boot_reason));
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memcpy((void *)MAILBOX_NX_BOOTLOADER_BOOT_REASON_BASE, &boot_reason, sizeof(boot_reason));
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/* Clean up. */
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free(bct);
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@ -335,7 +335,7 @@ void nxboot_main(void) {
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printf(u8"[NXBOOT]: Reading Exosphère...\n");
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/* Select the right address for Exosphère. */
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if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware <= EXOSPHERE_TARGET_FIRMWARE_400) {
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if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) {
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exosphere_memaddr = (void *)0x4002D000;
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} else {
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exosphere_memaddr = (void *)0x4002B000;
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@ -415,7 +415,7 @@ void nxboot_main(void) {
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if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) {
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MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2;
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} else {
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MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2_4X;
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MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X;
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}
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printf("[NXBOOT]: Powering on the CCPLEX...\n");
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@ -426,9 +426,6 @@ void nxboot_main(void) {
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/* Unmount everything. */
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nxfs_unmount_all();
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/* Turn off the backlight. */
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display_backlight(false);
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/* Terminate the display. */
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display_end();
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@ -3,11 +3,12 @@
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#include "utils.h"
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#define MAILBOX_NX_BOOTLOADER_BASE ((void *)(0x40002000))
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#define MAILBOX_NX_BOOTLOADER_BASE 0x40002000
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#define MAILBOX_NX_BOOTLOADER_BOOT_REASON_BASE (MAILBOX_NX_BOOTLOADER_BASE + 0xE10)
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#define MAKE_MAILBOX_NX_BOOTLOADER_REG(n) MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + n)
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#define MAILBOX_NX_BOOTLOADER_BOOT_REASON (MAILBOX_NX_BOOTLOADER_BASE + 0xE10)
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#define MAILBOX_NX_BOOTLOADER_SETUP_STATE MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + 0xEF8)
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#define MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + 0xEFC)
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#define MAILBOX_NX_BOOTLOADER_SETUP_STATE MAKE_MAILBOX_NX_BOOTLOADER_REG(0xEF8)
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#define MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE MAKE_MAILBOX_NX_BOOTLOADER_REG(0xEFC)
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#define NX_BOOTLOADER_STATE_INIT 0
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#define NX_BOOTLOADER_STATE_MOVED_BOOTCONFIG 1
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@ -5,13 +5,14 @@
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#define TIMERS_BASE 0x60005000
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#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
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#define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10)
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#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
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#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
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#define RTC_BASE 0x7000E000
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#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
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#define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08)
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#define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C)
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#define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10)
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#define RTC_SECONDS MAKE_RTC_REG(0x08)
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#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
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#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
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typedef struct {
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uint32_t CONFIG;
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#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
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#define WDT_REBOOT_PATTERN 0xC45A
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#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8*n)
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#define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
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void wait(uint32_t microseconds);
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