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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-23 04:12:02 +00:00
Implement a few TODOs with CAR driver.
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parent
5f7308efd1
commit
303e189559
3 changed files with 21 additions and 13 deletions
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@ -11,6 +11,9 @@
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#define MAKE_CAR_REG(n) (*((volatile uint32_t *)(CAR_BASE + n)))
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0 MAKE_CAR_REG(0x048)
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#define CLK_RST_CONTROLLER_RST_DEVICES_H_0 MAKE_CAR_REG(0x008)
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#define NUM_CAR_BANKS 7
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typedef enum {
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@ -1,5 +1,6 @@
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#include <string.h>
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#include "car.h"
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#include "fuse.h"
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#include "utils.h"
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#include "timers.h"
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@ -22,10 +23,7 @@ void fuse_init(void)
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/* Make all fuse registers visible */
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void fuse_make_regs_visible(void)
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{
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/* TODO: Replace this with a proper CLKRST driver */
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volatile uint32_t* misc_clk_reg = (volatile uint32_t *)MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_CLKRST) + 0x48;
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uint32_t misc_clk_val = *misc_clk_reg;
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*misc_clk_reg = (misc_clk_val | (1 << 28));
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CLK_RST_CONTROLLER_MISC_CLK_ENB_0 |= BIT(28);
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}
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/* Enable power to the fuse hardware array */
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@ -4,6 +4,7 @@
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#include "utils.h"
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#include "car.h"
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#include "bpmp.h"
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#include "arm.h"
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#include "configitem.h"
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@ -81,7 +82,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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unsigned int current_core = get_core_id();
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/* TODO: Enable clock and reset for I2C1. */
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clkrst_reboot(CARDEVICE_I2C1);
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if (configitem_should_profile_battery() && !i2c_query_ti_charger_bit_7()) {
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/* Profile the battery. */
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i2c_set_ti_charger_bit_7();
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@ -98,7 +99,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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wait(0x100);
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}
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}
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/* TODO: Reset I2C1 controller. */
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clkrst_disable(CARDEVICE_I2C1);
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/* Enable LP0 Wake Event Detection. */
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wait(75);
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@ -108,7 +109,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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APBDEV_PMC_WAKE2_STATUS_0 = 0xFFFFFFFF; /* Set all wake events. */
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wait(75);
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/* TODO: Enable I2C5 Clock/Reset. */
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clkrst_reboot(CARDEVICE_I2C5);
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if (fuse_get_bootrom_patch_version() >= 0x7F) {
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i2c_send_pmic_cpu_shutdown_cmd();
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}
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@ -131,8 +132,10 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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}
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}
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/* TODO: Jamais Vu mitigation #3: Ensure all relevant DMA controllers are held in reset. */
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/* This just requires checking CLK_RST_CONTROLLER_RST_DEVICES_H_0 & mask == 0x4000004. */
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/* Jamais Vu mitigation #3: Ensure all relevant DMA controllers are held in reset. */
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if ((CLK_RST_CONTROLLER_RST_DEVICES_H_0 & 0x4000004) != 0x4000004) {
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generic_panic();
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}
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/* Signal to bootrom the next reset should be a warmboot. */
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APBDEV_PMC_SCRATCH0_0 = 1;
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@ -153,11 +156,16 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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BPMP_VECTOR_IRQ = 0x40003004; /* Reboot. */
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BPMP_VECTOR_FIQ = 0x40003004; /* Reboot. */
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/* TODO: Hold the BPMP in reset. */
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/* Hold the BPMP in reset. */
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clkrst_disable(CARDEVICE_BPMP);
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/* Copy BPMP firmware. */
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uint8_t *lp0_entry_code = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_LP0_ENTRY_CODE));
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memcpy(lp0_entry_code, bpmpfw_bin, bpmpfw_bin_size);
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flush_dcache_range(lp0_entry_code, lp0_entry_code + bpmpfw_bin_size);
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/* TODO: Take the BPMP out of reset. */
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/* Take the BPMP out of reset. */
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clkrst_enable(CARDEVICE_BPMP);
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/* Start executing BPMP firmware. */
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0;
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@ -173,6 +181,5 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
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set_current_core_inactive();
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call_with_stack_pointer(get_smc_core012_stack_address(), save_se_and_power_down_cpu);
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/* NOTE: This return never actually occurs. */
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return 0;
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generic_panic();
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}
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