fusee_cpp: implement SDRAM initialization

fusee_cpp/program/program_ovl.ld

@@ -10,9 +10,13 @@ SECTIONS {
     OVERLAY : NOCROSSREFS {
         .ovl_sein {
             fusee_secure_initialize.o(.text*);
+            fusee_sdram.o(.text*);
             fusee_secure_initialize.o(.rodata*);
+            fusee_sdram.o(.rodata*);
             fusee_secure_initialize.o(.data*);
+            fusee_sdram.o(.data*);
             fusee_secure_initialize.o(.bss*);
+            fusee_sdram.o(.bss*);
             FILL(0x00000000)
             . = ORIGIN(ovl) + LENGTH(ovl) - 1;
             BYTE(0x00);

fusee_cpp/program/source/fusee_main.cpp

@@ -15,6 +15,7 @@
  */
 #include <exosphere.hpp>
 #include "fusee_secure_initialize.hpp"
+#include "fusee_sdram.hpp"
 
 namespace ams::nxboot {
 
@@ -22,6 +23,9 @@ namespace ams::nxboot {
         /* Perform secure hardware initialization. */
         SecureInitialize(true);
 
+        /* Initialize Sdram. */
+        InitializeSdram();
+
         /* TODO */
         AMS_INFINITE_LOOP();
     }

fusee_cpp/program/source/fusee_sdram.cpp

@@ -0,0 +1,970 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "fusee_sdram.hpp"
+#include "fusee_uncompress.hpp"
+
+namespace ams::nxboot {
+
+    namespace {
+
+        template<fuse::SocType SocType>
+        struct SdramParamsImpl;
+
+        template<> struct SdramParamsImpl<fuse::SocType_Erista> { using Type = br::erista::BootSdramParams; };
+        template<> struct SdramParamsImpl<fuse::SocType_Mariko> { using Type = br::mariko::BootSdramParams; };
+
+        template<fuse::SocType SocType>
+        using BootSdramParams = SdramParamsImpl<SocType>::Type;
+
+        constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
+        constexpr inline const uintptr_t PMC    = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
+        constexpr inline const uintptr_t APB    = secmon::MemoryRegionPhysicalDeviceApbMisc.GetAddress();
+        constexpr inline const uintptr_t MC     = secmon::MemoryRegionPhysicalDeviceMemoryController.GetAddress();
+        constexpr inline const uintptr_t EMC    = EMC_ADDRESS(0);
+        constexpr inline const uintptr_t AHB    = AHB_ARBC(0);
+
+        #include "fusee_sdram_params.inc"
+
+        void *GetSdramParams(fuse::SocType soc_type) {
+            /* Get DRAM Id. */
+            const auto dram_id = fuse::GetDramId();
+
+            /* Extract to work buffer. */
+            void *sdram_params_work_buffer = reinterpret_cast<void *>(0x4003D000);
+
+            if (soc_type == fuse::SocType_Erista) {
+                #define HANDLE_DRAM_CASE(_DRAM_ID_, _INDEX_)                                                                                                                 \
+                    case _DRAM_ID_:                                                                                                                                          \
+                        Uncompress(sdram_params_work_buffer, sizeof(BootSdramParams<fuse::SocType_Erista>), SdramParamsErista##_INDEX_, sizeof(SdramParamsErista##_INDEX_)); \
+                        break;
+                switch (dram_id) {
+                    HANDLE_DRAM_CASE(0, 0)
+                    HANDLE_DRAM_CASE(1, 1)
+                    HANDLE_DRAM_CASE(2, 2)
+                    HANDLE_DRAM_CASE(3, 3)
+                    HANDLE_DRAM_CASE(4, 4)
+                    HANDLE_DRAM_CASE(5, 5)
+                    HANDLE_DRAM_CASE(6, 6)
+                    default:
+                        AMS_ABORT("Invalid DRAM id");
+                }
+                #undef HANDLE_DRAM_CASE
+
+                return static_cast<BootSdramParams<fuse::SocType_Erista> *>(sdram_params_work_buffer);
+            } else /* if (soc_type == fuse::SocType_Mariko) */ {
+                #define HANDLE_DRAM_CASE(_DRAM_ID_, _INDEX_)                                                                                                                 \
+                    case _DRAM_ID_:                                                                                                                                          \
+                        Uncompress(sdram_params_work_buffer, sizeof(BootSdramParams<fuse::SocType_Mariko>), SdramParamsMariko##_INDEX_, sizeof(SdramParamsMariko##_INDEX_)); \
+                        break;
+                switch (dram_id) {
+                    HANDLE_DRAM_CASE( 3, 12)
+                    HANDLE_DRAM_CASE( 7,  0)
+                    HANDLE_DRAM_CASE( 8,  1)
+                    HANDLE_DRAM_CASE( 9,  2)
+                    HANDLE_DRAM_CASE(10,  3)
+                    HANDLE_DRAM_CASE(11,  4)
+                    HANDLE_DRAM_CASE(12,  1)
+                    HANDLE_DRAM_CASE(13,  2)
+                    HANDLE_DRAM_CASE(14,  3)
+                    HANDLE_DRAM_CASE(15,  4)
+                    HANDLE_DRAM_CASE(16,  5)
+                    HANDLE_DRAM_CASE(17,  6)
+                    HANDLE_DRAM_CASE(18,  7)
+                    HANDLE_DRAM_CASE(19,  6)
+                    HANDLE_DRAM_CASE(20,  8)
+                    HANDLE_DRAM_CASE(21,  9)
+                    HANDLE_DRAM_CASE(22, 10)
+                    HANDLE_DRAM_CASE(23,  7)
+                    HANDLE_DRAM_CASE(24,  6)
+                    HANDLE_DRAM_CASE(25, 11)
+                    HANDLE_DRAM_CASE(26, 11)
+                    HANDLE_DRAM_CASE(27, 11)
+                    HANDLE_DRAM_CASE(28,  7)
+                    default:
+                        AMS_ABORT("Invalid DRAM id");
+                }
+                #undef HANDLE_DRAM_CASE
+
+                return static_cast<BootSdramParams<fuse::SocType_Mariko> *>(sdram_params_work_buffer);
+            }
+        }
+
+        template<fuse::SocType SocType>
+        void SpareWrite(u32 reg, u32 value) {
+            if (reg) {
+                if constexpr (SocType == fuse::SocType_Erista) {
+                    reg::Write(reinterpret_cast<volatile u32 *>(reg), value);
+                } else if constexpr (SocType == fuse::SocType_Mariko) {
+                    /* TODO: Validate the write. */
+                    reg::Write(reinterpret_cast<volatile u32 *>(reg), value);
+                }
+            }
+        }
+
+        template<fuse::SocType SocType>
+        void InitializeSdramImpl(BootSdramParams<SocType> *params) {
+            /* Perform initial soc-specific setup. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                /* Enable sel_dpd on unused pins. */
+                reg::Write(PMC + APBDEV_PMC_IO_DPD3_REQ, (((params->EmcPmcScratch1 & 0x3FFFFFFF) | 0x80000000) ^ 0xFFFF) & 0xC000FFFF);
+                util::WaitMicroSeconds(params->PmcIoDpd3ReqWait);
+
+                /* Disable e_dpd_vttgen. */
+                u32 dpd4 = (params->EmcPmcScratch2 & 0x3FFFFFFF) | 0x80000000;
+                reg::Write(PMC + APBDEV_PMC_IO_DPD4_REQ, (dpd4 ^ 0x3FFF0000) & 0xFFFF0000);
+                util::WaitMicroSeconds(params->PmcIoDpd4ReqWait);
+
+                /* Disable e_dpd_bg. */
+                reg::Write(PMC + APBDEV_PMC_IO_DPD4_REQ, (dpd4 ^ 0x0000FFFF) & 0xC000FFFF);
+                util::WaitMicroSeconds(params->PmcIoDpd4ReqWait);
+
+                reg::Write(PMC + APBDEV_PMC_WEAK_BIAS, 0);
+                util::WaitMicroSeconds(1);
+
+                /* Enable memory clock. */
+                {
+                    /* Initialize pllm. */
+                    {
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC1, params->PllMSetupControl);
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, 0);
+
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM (PLLM_BASE_PLLM_ENABLE,                     DISABLE),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVP,       params->PllMPostDivider),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVN,   params->PllMFeedbackDivider),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVM,      params->PllMInputDivider));
+
+
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM (PLLM_BASE_PLLM_ENABLE,                      ENABLE),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVP,       params->PllMPostDivider),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVN,   params->PllMFeedbackDivider),
+                                                                          CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVM,      params->PllMInputDivider));
+
+                        /* Wait 300us ffor stability. */
+                        const auto stable_time = util::GetMicroSeconds() + 300;
+                        while (true) {
+                            if (reg::HasValue(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM(PLLM_BASE_PLLM_LOCK, LOCK))) {
+                                util::WaitMicroSeconds(10);
+                                break;
+                            }
+
+                            if (util::GetMicroSeconds() >= stable_time) {
+                                break;
+                            }
+                        }
+                    }
+
+                    /* Set CLK_SOURCE_EMC, using McEmcmArbMisc0 as MC_EMC_SAME_FREQ. */
+                    reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, (params->EmcClockSource & ~0x10000) | ((params->McEmemArbMisc0 >> 11) & 0x10000));
+
+                    if (params->EmcClockSourceDll) {
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL, params->EmcClockSourceDll);
+                    }
+
+                    if (params->ClearClk2Mc1) {
+                        reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_W_CLR, CLK_RST_REG_BITS_ENUM(CLK_ENB_W_CLK_ENB_MC1, ENABLE));
+                    }
+
+                    /* Enable EMC/Mem. */
+                    reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_H_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLK_ENB_EMC, ENABLE),
+                                                                          CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLK_ENB_MEM, ENABLE));
+
+                    /* Enable EMC DLL. */
+                    reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_ENB_X_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_X_CLK_ENB_EMC_DLL, ENABLE));
+                }
+
+                /* Clear reset for MEM/EMC. */
+                reg::Write(CLKRST + CLK_RST_CONTROLLER_RST_DEV_H_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_H_EMC_RST, ENABLE),
+                                                                      CLK_RST_REG_BITS_ENUM(RST_DEV_H_MEM_RST, ENABLE));
+
+                /* Set pad macros. */
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_0, params->EmcPmacroVttgenCtrl0);
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_1, params->EmcPmacroVttgenCtrl1);
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_2, params->EmcPmacroVttgenCtrl2);
+
+                reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+                util::WaitMicroSeconds(1);
+
+                /* Select EMC write mux. */
+                reg::Write(EMC + EMC_DBG, params->EmcDbg | reg::EncodeValue(EMC_REG_BITS_VALUE(DBG_WRITE_MUX, params->EmcDbgWriteMux)));
+
+                /* Patch 2. */
+                SpareWrite<SocType>(params->EmcBctSpare2, params->EmcBctSpare3);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                /* Patch 1 */
+                SpareWrite<SocType>(params->EmcBctSpare0, params->EmcBctSpare1);
+
+                if (params->ClkRstControllerPllmMisc2OverrideEnable) {
+                    reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, params->ClkRstControllerPllmMisc2Override);
+                }
+
+                /* Enable sel_dpd on unused pins. */
+                {
+                    u32 val = (~params->EmcPmcScratch1 & 0x00000FFF) << 18;
+                    val |= ((~params->EmcPmcScratch1 & 0x00001000) << 19) | ((~params->EmcPmcScratch1 & 0x00008000) << 15);
+                    reg::Write(PMC + APBDEV_PMC_WEAK_BIAS, val);
+                }
+
+                reg::Write(PMC + APBDEV_PMC_IO_DPD3_REQ, 0x80000000 | (~params->EmcPmcScratch1 & 0x00009FFF));
+                util::WaitMicroSeconds(params->PmcIoDpd3ReqWait);
+
+                /* Disable e_dpd_vttgen. */
+                reg::Write(PMC + APBDEV_PMC_IO_DPD4_REQ, 0x80000000 | (~params->EmcPmcScratch2 & 0x3FFF0000));
+                util::WaitMicroSeconds(params->PmcIoDpd4ReqWait);
+
+                /* Disable e_dpd_bg. */
+                reg::Write(PMC + APBDEV_PMC_IO_DPD4_REQ, 0x80000000 | (~params->EmcPmcScratch2 & 0x00001FFF));
+                util::WaitMicroSeconds(1);
+            }
+
+            /* Common phase 1. */
+
+            /* Program CMD mapping. */
+            reg::Write(EMC + EMC_FBIO_CFG7, params->EmcFbioCfg7);
+
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD0_0, params->EmcCmdMappingCmd0_0);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD0_1, params->EmcCmdMappingCmd0_1);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD0_2, params->EmcCmdMappingCmd0_2);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD1_0, params->EmcCmdMappingCmd1_0);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD1_1, params->EmcCmdMappingCmd1_1);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD1_2, params->EmcCmdMappingCmd1_2);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD2_0, params->EmcCmdMappingCmd2_0);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD2_1, params->EmcCmdMappingCmd2_1);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD2_2, params->EmcCmdMappingCmd2_2);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD3_0, params->EmcCmdMappingCmd3_0);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD3_1, params->EmcCmdMappingCmd3_1);
+            reg::Write(EMC + EMC_CMD_MAPPING_CMD3_2, params->EmcCmdMappingCmd3_2);
+            reg::Write(EMC + EMC_CMD_MAPPING_BYTE, params->EmcCmdMappingByte);
+
+            /* Program brick mapping. */
+            reg::Write(EMC + EMC_PMACRO_BRICK_MAPPING_0, params->EmcPmacroBrickMapping0);
+            reg::Write(EMC + EMC_PMACRO_BRICK_MAPPING_1, params->EmcPmacroBrickMapping1);
+            reg::Write(EMC + EMC_PMACRO_BRICK_MAPPING_2, params->EmcPmacroBrickMapping2);
+
+            /* Specific phase 2. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU1, (params->EmcPmacroBrickCtrlRfu1 | ~0x01120112) & 0x1FFF1FFF);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                /* Set pad macros. */
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_0, params->EmcPmacroVttgenCtrl0);
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_1, params->EmcPmacroVttgenCtrl1);
+                reg::Write(EMC + EMC_PMACRO_VTTGEN_CTRL_2, params->EmcPmacroVttgenCtrl2);
+
+                /* Set pad macro bias. */
+                reg::Write(EMC + EMC_PMACRO_BG_BIAS_CTRL_0, params->EmcPmacroBgBiasCtrl0);
+
+                SpareWrite<SocType>(params->EmcBctSpareSecure0, params->EmcBctSpareSecure1);
+                SpareWrite<SocType>(params->EmcBctSpareSecure2, params->EmcBctSpareSecure3);
+                SpareWrite<SocType>(params->EmcBctSpareSecure4, params->EmcBctSpareSecure5);
+
+                /* Trigger timing update. */
+                reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+                util::WaitMicroSeconds(params->PmcVddpSelWait + 2);
+
+                /* Set clock sources. */
+                reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, params->EmcClockSource);
+                reg::Write(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL, params->EmcClockSourceDll);
+
+                /* Select EMC write mux. */
+                reg::Write(EMC + EMC_DBG, params->EmcDbg | reg::EncodeValue(EMC_REG_BITS_VALUE(DBG_WRITE_MUX, params->EmcDbgWriteMux)));
+
+                /* Patch 2. */
+                SpareWrite<SocType>(params->EmcBctSpare2, params->EmcBctSpare3);
+            }
+
+            /* Common phase 2. */
+            reg::Write(EMC + EMC_CONFIG_SAMPLE_DELAY, params->EmcConfigSampleDelay);
+            reg::Write(EMC + EMC_FBIO_CFG8, params->EmcFbioCfg8);
+
+            /* Program swizzle registers. */
+            reg::Write(EMC + EMC_SWIZZLE_RANK0_BYTE0, params->EmcSwizzleRank0Byte0);
+            reg::Write(EMC + EMC_SWIZZLE_RANK0_BYTE1, params->EmcSwizzleRank0Byte1);
+            reg::Write(EMC + EMC_SWIZZLE_RANK0_BYTE2, params->EmcSwizzleRank0Byte2);
+            reg::Write(EMC + EMC_SWIZZLE_RANK0_BYTE3, params->EmcSwizzleRank0Byte3);
+            reg::Write(EMC + EMC_SWIZZLE_RANK1_BYTE0, params->EmcSwizzleRank1Byte0);
+            reg::Write(EMC + EMC_SWIZZLE_RANK1_BYTE1, params->EmcSwizzleRank1Byte1);
+            reg::Write(EMC + EMC_SWIZZLE_RANK1_BYTE2, params->EmcSwizzleRank1Byte2);
+            reg::Write(EMC + EMC_SWIZZLE_RANK1_BYTE3, params->EmcSwizzleRank1Byte3);
+
+            /* Patch 3. */
+            SpareWrite<SocType>(params->EmcBctSpare6, params->EmcBctSpare7);
+
+            /* Program pad controls. */
+            reg::Write(EMC + EMC_XM2COMPPADCTRL, params->EmcXm2CompPadCtrl);
+            reg::Write(EMC + EMC_XM2COMPPADCTRL2, params->EmcXm2CompPadCtrl2);
+            reg::Write(EMC + EMC_XM2COMPPADCTRL3, params->EmcXm2CompPadCtrl3);
+
+            /* Program autocal controls with shadowed register fields. */
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG2, params->EmcAutoCalConfig2);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG3, params->EmcAutoCalConfig3);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG4, params->EmcAutoCalConfig4);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG5, params->EmcAutoCalConfig5);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG6, params->EmcAutoCalConfig6);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG7, params->EmcAutoCalConfig7);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG8, params->EmcAutoCalConfig8);
+
+            reg::Write(EMC + EMC_PMACRO_RX_TERM, params->EmcPmacroRxTerm);
+            reg::Write(EMC + EMC_PMACRO_DQ_TX_DRV, params->EmcPmacroDqTxDrv);
+            reg::Write(EMC + EMC_PMACRO_CA_TX_DRV, params->EmcPmacroCaTxDrv);
+            reg::Write(EMC + EMC_PMACRO_CMD_TX_DRV, params->EmcPmacroCmdTxDrv);
+            reg::Write(EMC + EMC_PMACRO_AUTOCAL_CFG_COMMON, params->EmcPmacroAutocalCfgCommon);
+            reg::Write(EMC + EMC_AUTO_CAL_CHANNEL, params->EmcAutoCalChannel);
+            reg::Write(EMC + EMC_PMACRO_ZCTRL, params->EmcPmacroZctrl);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_DLL_CFG_0, params->EmcDllCfg0);
+                reg::Write(EMC + EMC_DLL_CFG_1, params->EmcDllCfg1);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_DLL_CFG_0, params->EmcPmacroDllCfg0);
+                reg::Write(EMC + EMC_PMACRO_DLL_CFG_1, params->EmcPmacroDllCfg1);
+            }
+
+            reg::Write(EMC + EMC_CFG_DIG_DLL_1, params->EmcCfgDigDll_1);
+
+            reg::Write(EMC + EMC_DATA_BRLSHFT_0, params->EmcDataBrlshft0);
+            reg::Write(EMC + EMC_DATA_BRLSHFT_1, params->EmcDataBrlshft1);
+            reg::Write(EMC + EMC_DQS_BRLSHFT_0, params->EmcDqsBrlshft0);
+            reg::Write(EMC + EMC_DQS_BRLSHFT_1, params->EmcDqsBrlshft1);
+            reg::Write(EMC + EMC_CMD_BRLSHFT_0, params->EmcCmdBrlshft0);
+            reg::Write(EMC + EMC_CMD_BRLSHFT_1, params->EmcCmdBrlshft1);
+            reg::Write(EMC + EMC_CMD_BRLSHFT_2, params->EmcCmdBrlshft2);
+            reg::Write(EMC + EMC_CMD_BRLSHFT_3, params->EmcCmdBrlshft3);
+            reg::Write(EMC + EMC_QUSE_BRLSHFT_0, params->EmcQuseBrlshft0);
+            reg::Write(EMC + EMC_QUSE_BRLSHFT_1, params->EmcQuseBrlshft1);
+            reg::Write(EMC + EMC_QUSE_BRLSHFT_2, params->EmcQuseBrlshft2);
+            reg::Write(EMC + EMC_QUSE_BRLSHFT_3, params->EmcQuseBrlshft3);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU1, (params->EmcPmacroBrickCtrlRfu1 | ~0x01BF01BF) & 0x1FFF1FFF);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU1, params->EmcPmacroBrickCtrlRfu1);
+            }
+
+            reg::Write(EMC + EMC_PMACRO_PAD_CFG_CTRL, params->EmcPmacroPadCfgCtrl);
+            reg::Write(EMC + EMC_PMACRO_CMD_BRICK_CTRL_FDPD, params->EmcPmacroCmdBrickCtrlFdpd);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU2, params->EmcPmacroBrickCtrlRfu2 & 0xFF7FFF7F);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU2, params->EmcPmacroBrickCtrlRfu2);
+            }
+
+            reg::Write(EMC + EMC_PMACRO_DATA_BRICK_CTRL_FDPD, params->EmcPmacroDataBrickCtrlFdpd);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_BG_BIAS_CTRL_0, params->EmcPmacroBgBiasCtrl0);
+            }
+
+            reg::Write(EMC + EMC_PMACRO_DATA_PAD_RX_CTRL, params->EmcPmacroDataPadRxCtrl);
+            reg::Write(EMC + EMC_PMACRO_CMD_PAD_RX_CTRL, params->EmcPmacroCmdPadRxCtrl);
+            reg::Write(EMC + EMC_PMACRO_DATA_PAD_TX_CTRL, params->EmcPmacroDataPadTxCtrl);
+            reg::Write(EMC + EMC_PMACRO_DATA_RX_TERM_MODE, params->EmcPmacroDataRxTermMode);
+            reg::Write(EMC + EMC_PMACRO_CMD_RX_TERM_MODE, params->EmcPmacroCmdRxTermMode);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_CMD_PAD_TX_CTRL, params->EmcPmacroCmdPadTxCtrl);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_CMD_PAD_TX_CTRL, params->EmcPmacroCmdPadTxCtrl & 0xEFFFFFFF);
+            }
+
+            reg::Write(EMC + EMC_CFG_3, params->EmcCfg3);
+
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_0, params->EmcPmacroTxPwrd0);
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_1, params->EmcPmacroTxPwrd1);
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_2, params->EmcPmacroTxPwrd2);
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_3, params->EmcPmacroTxPwrd3);
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_4, params->EmcPmacroTxPwrd4);
+            reg::Write(EMC + EMC_PMACRO_TX_PWRD_5, params->EmcPmacroTxPwrd5);
+
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_0, params->EmcPmacroTxSelClkSrc0);
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_1, params->EmcPmacroTxSelClkSrc1);
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_2, params->EmcPmacroTxSelClkSrc2);
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_3, params->EmcPmacroTxSelClkSrc3);
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_4, params->EmcPmacroTxSelClkSrc4);
+            reg::Write(EMC + EMC_PMACRO_TX_SEL_CLK_SRC_5, params->EmcPmacroTxSelClkSrc5);
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_0, params->EmcPmacroPerbitFgcgCtrl0);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_1, params->EmcPmacroPerbitFgcgCtrl1);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_2, params->EmcPmacroPerbitFgcgCtrl2);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_3, params->EmcPmacroPerbitFgcgCtrl3);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_4, params->EmcPmacroPerbitFgcgCtrl4);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_FGCG_CTRL_5, params->EmcPmacroPerbitFgcgCtrl5);
+
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_0, params->EmcPmacroPerbitRfuCtrl0);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_1, params->EmcPmacroPerbitRfuCtrl1);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_2, params->EmcPmacroPerbitRfuCtrl2);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_3, params->EmcPmacroPerbitRfuCtrl3);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_4, params->EmcPmacroPerbitRfuCtrl4);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU_CTRL_5, params->EmcPmacroPerbitRfuCtrl5);
+
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_0, params->EmcPmacroPerbitRfu1Ctrl0);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_1, params->EmcPmacroPerbitRfu1Ctrl1);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_2, params->EmcPmacroPerbitRfu1Ctrl2);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_3, params->EmcPmacroPerbitRfu1Ctrl3);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_4, params->EmcPmacroPerbitRfu1Ctrl4);
+                reg::Write(EMC + EMC_PMACRO_PERBIT_RFU1_CTRL_5, params->EmcPmacroPerbitRfu1Ctrl5);
+
+                reg::Write(EMC + EMC_PMACRO_DATA_PI_CTRL, params->EmcPmacroDataPiCtrl);
+                reg::Write(EMC + EMC_PMACRO_CMD_PI_CTRL, params->EmcPmacroCmdPiCtrl);
+            }
+
+            reg::Write(EMC + EMC_PMACRO_DDLL_BYPASS, params->EmcPmacroDdllBypass);
+            reg::Write(EMC + EMC_PMACRO_DDLL_PWRD_0, params->EmcPmacroDdllPwrd0);
+            reg::Write(EMC + EMC_PMACRO_DDLL_PWRD_1, params->EmcPmacroDdllPwrd1);
+            reg::Write(EMC + EMC_PMACRO_DDLL_PWRD_2, params->EmcPmacroDdllPwrd2);
+            reg::Write(EMC + EMC_PMACRO_CMD_CTRL_0, params->EmcPmacroCmdCtrl0);
+            reg::Write(EMC + EMC_PMACRO_CMD_CTRL_1, params->EmcPmacroCmdCtrl1);
+            reg::Write(EMC + EMC_PMACRO_CMD_CTRL_2, params->EmcPmacroCmdCtrl2);
+            reg::Write(EMC + EMC_PMACRO_IB_VREF_DQ_0, params->EmcPmacroIbVrefDq_0);
+            reg::Write(EMC + EMC_PMACRO_IB_VREF_DQ_1, params->EmcPmacroIbVrefDq_1);
+            reg::Write(EMC + EMC_PMACRO_IB_VREF_DQS_0, params->EmcPmacroIbVrefDqs_0);
+            reg::Write(EMC + EMC_PMACRO_IB_VREF_DQS_1, params->EmcPmacroIbVrefDqs_1);
+            reg::Write(EMC + EMC_PMACRO_IB_RXRT, params->EmcPmacroIbRxrt);
+
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_0, params->EmcPmacroQuseDdllRank0_0);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_1, params->EmcPmacroQuseDdllRank0_1);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_2, params->EmcPmacroQuseDdllRank0_2);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_3, params->EmcPmacroQuseDdllRank0_3);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_4, params->EmcPmacroQuseDdllRank0_4);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK0_5, params->EmcPmacroQuseDdllRank0_5);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_0, params->EmcPmacroQuseDdllRank1_0);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_1, params->EmcPmacroQuseDdllRank1_1);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_2, params->EmcPmacroQuseDdllRank1_2);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_3, params->EmcPmacroQuseDdllRank1_3);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_4, params->EmcPmacroQuseDdllRank1_4);
+            reg::Write(EMC + EMC_PMACRO_QUSE_DDLL_RANK1_5, params->EmcPmacroQuseDdllRank1_5);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU1, params->EmcPmacroBrickCtrlRfu1);
+            }
+
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0, params->EmcPmacroObDdllLongDqRank0_0);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1, params->EmcPmacroObDdllLongDqRank0_1);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2, params->EmcPmacroObDdllLongDqRank0_2);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3, params->EmcPmacroObDdllLongDqRank0_3);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4, params->EmcPmacroObDdllLongDqRank0_4);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5, params->EmcPmacroObDdllLongDqRank0_5);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0, params->EmcPmacroObDdllLongDqRank1_0);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1, params->EmcPmacroObDdllLongDqRank1_1);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2, params->EmcPmacroObDdllLongDqRank1_2);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3, params->EmcPmacroObDdllLongDqRank1_3);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4, params->EmcPmacroObDdllLongDqRank1_4);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5, params->EmcPmacroObDdllLongDqRank1_5);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0, params->EmcPmacroObDdllLongDqsRank0_0);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1, params->EmcPmacroObDdllLongDqsRank0_1);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2, params->EmcPmacroObDdllLongDqsRank0_2);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3, params->EmcPmacroObDdllLongDqsRank0_3);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4, params->EmcPmacroObDdllLongDqsRank0_4);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5, params->EmcPmacroObDdllLongDqsRank0_5);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0, params->EmcPmacroObDdllLongDqsRank1_0);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1, params->EmcPmacroObDdllLongDqsRank1_1);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2, params->EmcPmacroObDdllLongDqsRank1_2);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3, params->EmcPmacroObDdllLongDqsRank1_3);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4, params->EmcPmacroObDdllLongDqsRank1_4);
+            reg::Write(EMC + EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5, params->EmcPmacroObDdllLongDqsRank1_5);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0, params->EmcPmacroIbDdllLongDqsRank0_0);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1, params->EmcPmacroIbDdllLongDqsRank0_1);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2, params->EmcPmacroIbDdllLongDqsRank0_2);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3, params->EmcPmacroIbDdllLongDqsRank0_3);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0, params->EmcPmacroIbDdllLongDqsRank1_0);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1, params->EmcPmacroIbDdllLongDqsRank1_1);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2, params->EmcPmacroIbDdllLongDqsRank1_2);
+            reg::Write(EMC + EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3, params->EmcPmacroIbDdllLongDqsRank1_3);
+
+            reg::Write(EMC + EMC_PMACRO_DDLL_LONG_CMD_0, params->EmcPmacroDdllLongCmd_0);
+            reg::Write(EMC + EMC_PMACRO_DDLL_LONG_CMD_1, params->EmcPmacroDdllLongCmd_1);
+            reg::Write(EMC + EMC_PMACRO_DDLL_LONG_CMD_2, params->EmcPmacroDdllLongCmd_2);
+            reg::Write(EMC + EMC_PMACRO_DDLL_LONG_CMD_3, params->EmcPmacroDdllLongCmd_3);
+            reg::Write(EMC + EMC_PMACRO_DDLL_LONG_CMD_4, params->EmcPmacroDdllLongCmd_4);
+            reg::Write(EMC + EMC_PMACRO_DDLL_SHORT_CMD_0, params->EmcPmacroDdllShortCmd_0);
+            reg::Write(EMC + EMC_PMACRO_DDLL_SHORT_CMD_1, params->EmcPmacroDdllShortCmd_1);
+            reg::Write(EMC + EMC_PMACRO_DDLL_SHORT_CMD_2, params->EmcPmacroDdllShortCmd_2);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_COMMON_PAD_TX_CTRL, (params->EmcPmacroCommonPadTxCtrl | ~0x1) & 0xF);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_DDLL_PERIODIC_OFFSET, params->EmcPmacroDdllPeriodicOffset);
+            }
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                SpareWrite<SocType>(params->EmcBctSpare4, params->EmcBctSpare5);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                SpareWrite<SocType>(params->EmcBctSpare4, params->EmcBctSpare5);
+                SpareWrite<SocType>(params->EmcBctSpareSecure6, params->EmcBctSpareSecure7);
+                SpareWrite<SocType>(params->EmcBctSpareSecure8, params->EmcBctSpareSecure9);
+                SpareWrite<SocType>(params->EmcBctSpareSecure10, params->EmcBctSpareSecure11);
+            }
+
+            reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+
+            /* Initialize MC VPR settings. */
+            reg::Write(MC + MC_VIDEO_PROTECT_BOM, params->McVideoProtectBom);
+            reg::Write(MC + MC_VIDEO_PROTECT_BOM_ADR_HI, params->McVideoProtectBomAdrHi);
+            reg::Write(MC + MC_VIDEO_PROTECT_SIZE_MB, params->McVideoProtectSizeMb);
+            reg::Write(MC + MC_VIDEO_PROTECT_VPR_OVERRIDE, params->McVideoProtectVprOverride);
+            reg::Write(MC + MC_VIDEO_PROTECT_VPR_OVERRIDE1, params->McVideoProtectVprOverride1);
+            reg::Write(MC + MC_VIDEO_PROTECT_GPU_OVERRIDE_0, params->McVideoProtectGpuOverride0);
+            reg::Write(MC + MC_VIDEO_PROTECT_GPU_OVERRIDE_1, params->McVideoProtectGpuOverride1);
+
+            /* Program SDRAM geometry parameters. */
+            reg::Write(MC + MC_EMEM_ADR_CFG, params->McEmemAdrCfg);
+            reg::Write(MC + MC_EMEM_ADR_CFG_DEV0, params->McEmemAdrCfgDev0);
+            reg::Write(MC + MC_EMEM_ADR_CFG_DEV1, params->McEmemAdrCfgDev1);
+            reg::Write(MC + MC_EMEM_ADR_CFG_CHANNEL_MASK, params->McEmemAdrCfgChannelMask);
+
+            /* Program bank swizzling. */
+            reg::Write(MC + MC_EMEM_ADR_CFG_BANK_MASK_0, params->McEmemAdrCfgBankMask0);
+            reg::Write(MC + MC_EMEM_ADR_CFG_BANK_MASK_1, params->McEmemAdrCfgBankMask1);
+            reg::Write(MC + MC_EMEM_ADR_CFG_BANK_MASK_2, params->McEmemAdrCfgBankMask2);
+
+            /* Program external memory aperture (base and size). */
+            reg::Write(MC + MC_EMEM_CFG, params->McEmemCfg);
+
+            /* Program SEC carveout (base and size). */
+            reg::Write(MC + MC_SEC_CARVEOUT_BOM, params->McSecCarveoutBom);
+            reg::Write(MC + MC_SEC_CARVEOUT_ADR_HI, params->McSecCarveoutAdrHi);
+            reg::Write(MC + MC_SEC_CARVEOUT_SIZE_MB, params->McSecCarveoutSizeMb);
+
+            /* Program MTS carveout (base and size). */
+            reg::Write(MC + MC_MTS_CARVEOUT_BOM, params->McMtsCarveoutBom);
+            reg::Write(MC + MC_MTS_CARVEOUT_ADR_HI, params->McMtsCarveoutAdrHi);
+            reg::Write(MC + MC_MTS_CARVEOUT_SIZE_MB, params->McMtsCarveoutSizeMb);
+
+            /* Program the memory arbiter. */
+            reg::Write(MC + MC_EMEM_ARB_CFG, params->McEmemArbCfg);
+            reg::Write(MC + MC_EMEM_ARB_OUTSTANDING_REQ, params->McEmemArbOutstandingReq);
+            reg::Write(MC + MC_EMEM_ARB_REFPB_HP_CTRL, params->McEmemArbRefpbHpCtrl);
+            reg::Write(MC + MC_EMEM_ARB_REFPB_BANK_CTRL, params->McEmemArbRefpbBankCtrl);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RCD, params->McEmemArbTimingRcd);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RP, params->McEmemArbTimingRp);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RC, params->McEmemArbTimingRc);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RAS, params->McEmemArbTimingRas);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_FAW, params->McEmemArbTimingFaw);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RRD, params->McEmemArbTimingRrd);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RAP2PRE, params->McEmemArbTimingRap2Pre);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_WAP2PRE, params->McEmemArbTimingWap2Pre);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_R2R, params->McEmemArbTimingR2R);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_W2W, params->McEmemArbTimingW2W);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_CCDMW, params->McEmemArbTimingCcdmw);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_R2W, params->McEmemArbTimingR2W);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_W2R, params->McEmemArbTimingW2R);
+            reg::Write(MC + MC_EMEM_ARB_TIMING_RFCPB, params->McEmemArbTimingRFCPB);
+            reg::Write(MC + MC_EMEM_ARB_DA_TURNS, params->McEmemArbDaTurns);
+            reg::Write(MC + MC_EMEM_ARB_DA_COVERS, params->McEmemArbDaCovers);
+            reg::Write(MC + MC_EMEM_ARB_MISC0, params->McEmemArbMisc0);
+            reg::Write(MC + MC_EMEM_ARB_MISC1, params->McEmemArbMisc1);
+            reg::Write(MC + MC_EMEM_ARB_MISC2, params->McEmemArbMisc2);
+            reg::Write(MC + MC_EMEM_ARB_RING1_THROTTLE, params->McEmemArbRing1Throttle);
+            reg::Write(MC + MC_EMEM_ARB_OVERRIDE, params->McEmemArbOverride);
+            reg::Write(MC + MC_EMEM_ARB_OVERRIDE_1, params->McEmemArbOverride1);
+            reg::Write(MC + MC_EMEM_ARB_RSV, params->McEmemArbRsv);
+            reg::Write(MC + MC_DA_CONFIG0, params->McDaCfg0);
+
+            /* Trigger MC timing update. */
+            reg::Write(MC + MC_TIMING_CONTROL, 1);
+
+            /* Program second-level clock enable overrides. */
+            reg::Write(MC + MC_CLKEN_OVERRIDE, params->McClkenOverride);
+
+            /* Program statistics gathering. */
+            reg::Write(MC + MC_STAT_CONTROL, params->McStatControl);
+
+            /* Program SDRAM geometry parameters. */
+            reg::Write(EMC + EMC_ADR_CFG, params->EmcAdrCfg);
+
+            /* Program second-level clock enable overrides. */
+            reg::Write(EMC + EMC_CLKEN_OVERRIDE, params->EmcClkenOverride);
+
+            /* Program EMC pad auto calibration. */
+            reg::Write(EMC + EMC_PMACRO_AUTOCAL_CFG_0, params->EmcPmacroAutocalCfg0);
+            reg::Write(EMC + EMC_PMACRO_AUTOCAL_CFG_1, params->EmcPmacroAutocalCfg1);
+            reg::Write(EMC + EMC_PMACRO_AUTOCAL_CFG_2, params->EmcPmacroAutocalCfg2);
+
+            reg::Write(EMC + EMC_AUTO_CAL_VREF_SEL_0, params->EmcAutoCalVrefSel0);
+            reg::Write(EMC + EMC_AUTO_CAL_VREF_SEL_1, params->EmcAutoCalVrefSel1);
+
+            reg::Write(EMC + EMC_AUTO_CAL_INTERVAL, params->EmcAutoCalInterval);
+            reg::Write(EMC + EMC_AUTO_CAL_CONFIG, params->EmcAutoCalConfig);
+            util::WaitMicroSeconds(params->EmcAutoCalWait);
+
+            /* Patch 5. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                SpareWrite<SocType>(params->EmcBctSpare8, params->EmcBctSpare9);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                SpareWrite<SocType>(params->EmcBctSpare8, params->EmcBctSpare9);
+                reg::Write(EMC + EMC_AUTO_CAL_CONFIG9, params->EmcAutoCalConfig9);
+            }
+
+            /* Program EMC timing configuration. */
+            reg::Write(EMC + EMC_CFG_2, params->EmcCfg2);
+            reg::Write(EMC + EMC_CFG_PIPE, params->EmcCfgPipe);
+            reg::Write(EMC + EMC_CFG_PIPE_1, params->EmcCfgPipe1);
+            reg::Write(EMC + EMC_CFG_PIPE_2, params->EmcCfgPipe2);
+            reg::Write(EMC + EMC_CMDQ, params->EmcCmdQ);
+            reg::Write(EMC + EMC_MC2EMCQ, params->EmcMc2EmcQ);
+            reg::Write(EMC + EMC_MRS_WAIT_CNT, params->EmcMrsWaitCnt);
+            reg::Write(EMC + EMC_MRS_WAIT_CNT2, params->EmcMrsWaitCnt2);
+            reg::Write(EMC + EMC_FBIO_CFG5, params->EmcFbioCfg5);
+            reg::Write(EMC + EMC_RC, params->EmcRc);
+            reg::Write(EMC + EMC_RFC, params->EmcRfc);
+            reg::Write(EMC + EMC_RFCPB, params->EmcRfcPb);
+            reg::Write(EMC + EMC_REFCTRL2, params->EmcRefctrl2);
+            reg::Write(EMC + EMC_RFC_SLR, params->EmcRfcSlr);
+            reg::Write(EMC + EMC_RAS, params->EmcRas);
+            reg::Write(EMC + EMC_RP, params->EmcRp);
+            reg::Write(EMC + EMC_TPPD, params->EmcTppd);
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_TRTM, params->EmcTrtm);
+                reg::Write(EMC + EMC_TWTM, params->EmcTwtm);
+                reg::Write(EMC + EMC_TRATM, params->EmcTratm);
+                reg::Write(EMC + EMC_TWATM, params->EmcTwatm);
+                reg::Write(EMC + EMC_TR2REF, params->EmcTr2ref);
+            }
+
+            reg::Write(EMC + EMC_R2R, params->EmcR2r);
+            reg::Write(EMC + EMC_W2W, params->EmcW2w);
+            reg::Write(EMC + EMC_R2W, params->EmcR2w);
+            reg::Write(EMC + EMC_W2R, params->EmcW2r);
+            reg::Write(EMC + EMC_R2P, params->EmcR2p);
+            reg::Write(EMC + EMC_W2P, params->EmcW2p);
+            reg::Write(EMC + EMC_CCDMW, params->EmcCcdmw);
+            reg::Write(EMC + EMC_RD_RCD, params->EmcRdRcd);
+            reg::Write(EMC + EMC_WR_RCD, params->EmcWrRcd);
+            reg::Write(EMC + EMC_RRD, params->EmcRrd);
+            reg::Write(EMC + EMC_REXT, params->EmcRext);
+            reg::Write(EMC + EMC_WEXT, params->EmcWext);
+            reg::Write(EMC + EMC_WDV, params->EmcWdv);
+            reg::Write(EMC + EMC_WDV_CHK, params->EmcWdvChk);
+            reg::Write(EMC + EMC_WSV, params->EmcWsv);
+            reg::Write(EMC + EMC_WEV, params->EmcWev);
+            reg::Write(EMC + EMC_WDV_MASK, params->EmcWdvMask);
+            reg::Write(EMC + EMC_WS_DURATION, params->EmcWsDuration);
+            reg::Write(EMC + EMC_WE_DURATION, params->EmcWeDuration);
+            reg::Write(EMC + EMC_QUSE, params->EmcQUse);
+            reg::Write(EMC + EMC_QUSE_WIDTH, params->EmcQuseWidth);
+            reg::Write(EMC + EMC_IBDLY, params->EmcIbdly);
+            reg::Write(EMC + EMC_OBDLY, params->EmcObdly);
+            reg::Write(EMC + EMC_EINPUT, params->EmcEInput);
+            reg::Write(EMC + EMC_EINPUT_DURATION, params->EmcEInputDuration);
+            reg::Write(EMC + EMC_PUTERM_EXTRA, params->EmcPutermExtra);
+            reg::Write(EMC + EMC_PUTERM_WIDTH, params->EmcPutermWidth);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_PMACRO_COMMON_PAD_TX_CTRL, params->EmcPmacroCommonPadTxCtrl);
+            }
+
+            reg::Write(EMC + EMC_DBG, params->EmcDbg);
+            reg::Write(EMC + EMC_QRST, params->EmcQRst);
+            reg::Write(EMC + EMC_ISSUE_QRST, 1);
+            reg::Write(EMC + EMC_ISSUE_QRST, 0);
+            reg::Write(EMC + EMC_QSAFE, params->EmcQSafe);
+            reg::Write(EMC + EMC_RDV, params->EmcRdv);
+            reg::Write(EMC + EMC_RDV_MASK, params->EmcRdvMask);
+            reg::Write(EMC + EMC_RDV_EARLY, params->EmcRdvEarly);
+            reg::Write(EMC + EMC_RDV_EARLY_MASK, params->EmcRdvEarlyMask);
+            reg::Write(EMC + EMC_QPOP, params->EmcQpop);
+            reg::Write(EMC + EMC_REFRESH, params->EmcRefresh);
+            reg::Write(EMC + EMC_BURST_REFRESH_NUM, params->EmcBurstRefreshNum);
+            reg::Write(EMC + EMC_PRE_REFRESH_REQ_CNT, params->EmcPreRefreshReqCnt);
+            reg::Write(EMC + EMC_PDEX2WR, params->EmcPdEx2Wr);
+            reg::Write(EMC + EMC_PDEX2RD, params->EmcPdEx2Rd);
+            reg::Write(EMC + EMC_PCHG2PDEN, params->EmcPChg2Pden);
+            reg::Write(EMC + EMC_ACT2PDEN, params->EmcAct2Pden);
+            reg::Write(EMC + EMC_AR2PDEN, params->EmcAr2Pden);
+            reg::Write(EMC + EMC_RW2PDEN, params->EmcRw2Pden);
+            reg::Write(EMC + EMC_CKE2PDEN, params->EmcCke2Pden);
+            reg::Write(EMC + EMC_PDEX2CKE, params->EmcPdex2Cke);
+            reg::Write(EMC + EMC_PDEX2MRR, params->EmcPdex2Mrr);
+            reg::Write(EMC + EMC_TXSR, params->EmcTxsr);
+            reg::Write(EMC + EMC_TXSRDLL, params->EmcTxsrDll);
+            reg::Write(EMC + EMC_TCKE, params->EmcTcke);
+            reg::Write(EMC + EMC_TCKESR, params->EmcTckesr);
+            reg::Write(EMC + EMC_TPD, params->EmcTpd);
+            reg::Write(EMC + EMC_TFAW, params->EmcTfaw);
+            reg::Write(EMC + EMC_TRPAB, params->EmcTrpab);
+            reg::Write(EMC + EMC_TCLKSTABLE, params->EmcTClkStable);
+            reg::Write(EMC + EMC_TCLKSTOP, params->EmcTClkStop);
+            reg::Write(EMC + EMC_TREFBW, params->EmcTRefBw);
+            reg::Write(EMC + EMC_ODT_WRITE, params->EmcOdtWrite);
+            reg::Write(EMC + EMC_CFG_DIG_DLL, params->EmcCfgDigDll);
+            reg::Write(EMC + EMC_CFG_DIG_DLL_PERIOD, params->EmcCfgDigDllPeriod);
+
+            /* Lock bit written later for CFG_ADR_EN. */
+            reg::Write(EMC + EMC_FBIO_SPARE, params->EmcFbioSpare & 0xFFFFFFFD);
+            reg::Write(EMC + EMC_CFG_RSV, params->EmcCfgRsv);
+            reg::Write(EMC + EMC_PMC_SCRATCH1, params->EmcPmcScratch1);
+            reg::Write(EMC + EMC_PMC_SCRATCH2, params->EmcPmcScratch2);
+            reg::Write(EMC + EMC_PMC_SCRATCH3, params->EmcPmcScratch3);
+            reg::Write(EMC + EMC_ACPD_CONTROL, params->EmcAcpdControl);
+            reg::Write(EMC + EMC_TXDSRVTTGEN, params->EmcTxdsrvttgen);
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_DSR_VTTGEN_CTRL_0, params->EmcPmacroDsrVttgenCtrl0);
+            }
+
+            /* Set pipe bypass enable bits before sending any DRAM commands. */
+            reg::Write(EMC + EMC_CFG, (params->EmcCfg * 0xE) | 0x03C00000);
+
+            /* Perform bootrom patch. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                if (params->BootRomPatchControl & 0x80000000) {
+                    reg::Write(APB + ((params->BootRomPatchControl & 0x3FFFFFFF) << 2), params->BootRomPatchData);
+                    reg::Write(MC + MC_TIMING_CONTROL, 1);
+                }
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                if (params->BootRomPatchControl) {
+                    SpareWrite<SocType>(params->BootRomPatchControl, params->BootRomPatchData);
+                    reg::Write(MC + MC_TIMING_CONTROL, 1);
+                }
+
+                SpareWrite<SocType>(params->EmcBctSpareSecure12, params->EmcBctSpareSecure13);
+                SpareWrite<SocType>(params->EmcBctSpareSecure14, params->EmcBctSpareSecure15);
+                SpareWrite<SocType>(params->EmcBctSpareSecure16, params->EmcBctSpareSecure17);
+            }
+
+            /* Release SEL_DPD_CMD. */
+            reg::Write(PMC + APBDEV_PMC_IO_DPD3_REQ, ((params->EmcPmcScratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000);
+            util::WaitMicroSeconds(params->PmcIoDpd3ReqWait);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                if (params->EmcAutoCalInterval == 0) {
+                    reg::Write(EMC + EMC_AUTO_CAL_CONFIG, params->EmcAutoCalConfig | 0x200);
+                }
+
+                reg::Write(EMC + EMC_PMACRO_BRICK_CTRL_RFU2, params->EmcPmacroBrickCtrlRfu2);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_PMACRO_CMD_PAD_TX_CTRL, params->EmcPmacroCmdPadTxCtrl);
+            }
+
+            /* ZQ CAL setup */
+            if (params->EmcZcalWarmColdBootEnables & 1) {
+                if (params->MemoryType == br::BootMemoryType_Ddr3) {
+                    reg::Write(EMC + EMC_ZCAL_WAIT_CNT, params->EmcZcalWaitCnt << 3);
+                } else if (params->MemoryType == br::BootMemoryType_LpDdr4) {
+                    reg::Write(EMC + EMC_ZCAL_WAIT_CNT, params->EmcZcalWaitCnt);
+                    reg::Write(EMC + EMC_ZCAL_MRW_CMD, params->EmcZcalMrwCmd);
+                }
+            }
+
+            /* Trigger timing update. */
+            reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+            util::WaitMicroSeconds(params->EmcTimingControlWait);
+
+            /* Deassert HOLD_CKE_LOW. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::ClearBits(PMC + APBDEV_PMC_DDR_CNTRL, ~0xFFF8007F);
+            } else if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::ClearBits(PMC + APBDEV_PMC_DDR_CNTRL, ~0xFF78007F);
+            }
+
+            util::WaitMicroSeconds(params->PmcDdrCntrlWait);
+
+            /* Set clock enable signal. */
+            const u32 pin_gpio_cfg = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12);
+            if (params->MemoryType == br::BootMemoryType_Ddr3 || params->MemoryType == br::BootMemoryType_LpDdr4) {
+                reg::Write(EMC + EMC_PIN, pin_gpio_cfg);
+                reg::Read(EMC + EMC_PIN);
+                util::WaitMicroSeconds(200 + params->EmcPinExtraWait);
+
+                reg::Write(EMC + EMC_PIN, pin_gpio_cfg | 0x100);
+                reg::Read(EMC + EMC_PIN);
+
+                const u32 wait = params->MemoryType == br::BootMemoryType_Ddr3 ? 500 : 2000;
+                util::WaitMicroSeconds(wait + params->EmcPinExtraWait);
+            }
+
+            /* Set clock enable signal. */
+            reg::Write(EMC + EMC_PIN, pin_gpio_cfg | 0x101);
+            reg::Read(EMC + EMC_PIN);
+            util::WaitMicroSeconds(params->EmcPinProgramWait);
+
+            /* Send NOP */
+            if (params->MemoryType != br::BootMemoryType_LpDdr4) {
+                reg::Write(EMC + EMC_NOP, (params->EmcDevSelect << 30) | 1);
+            }
+
+            /* On coldboot with LPDDR2/3, wait 200us after asserting CKE high. */
+            if (params->MemoryType != br::BootMemoryType_LpDdr2) {
+                util::WaitMicroSeconds(200 + params->EmcPinExtraWait);
+            }
+
+            /* Init ZQ calibration. */
+            if (params->MemoryType == br::BootMemoryType_LpDdr4) {
+                SpareWrite<SocType>(params->EmcBctSpare10, params->EmcBctSpare11);
+
+                reg::Write(EMC + EMC_MRW2, params->EmcMrw2);
+                reg::Write(EMC + EMC_MRW, params->EmcMrw1);
+                reg::Write(EMC + EMC_MRW3, params->EmcMrw3);
+                reg::Write(EMC + EMC_MRW4, params->EmcMrw4);
+                reg::Write(EMC + EMC_MRW6, params->EmcMrw6);
+                reg::Write(EMC + EMC_MRW14, params->EmcMrw14);
+
+                reg::Write(EMC + EMC_MRW8, params->EmcMrw8);
+                reg::Write(EMC + EMC_MRW12, params->EmcMrw12);
+                reg::Write(EMC + EMC_MRW9, params->EmcMrw9);
+                reg::Write(EMC + EMC_MRW13, params->EmcMrw13);
+
+                if (params->EmcZcalWarmColdBootEnables & 1) {
+                    /* Issue ZQCAL start, device 0. */
+                    reg::Write(EMC + EMC_ZQ_CAL, params->EmcZcalInitDev0);
+                    util::WaitMicroSeconds(params->EmcZcalInitWait);
+
+                    /* Issue ZQCAL latch. */
+                    reg::Write(EMC + EMC_ZQ_CAL, params->EmcZcalInitDev0 ^ 0x3);
+
+                    /* Do the same for device 1. */
+                    if ((params->EmcDevSelect & 2) == 0) {
+                        reg::Write(EMC + EMC_ZQ_CAL, params->EmcZcalInitDev1);
+                        util::WaitMicroSeconds(params->EmcZcalInitWait);
+
+                        reg::Write(EMC + EMC_ZQ_CAL, params->EmcZcalInitDev1 ^ 0x3);
+                    }
+                }
+            }
+
+            /* Patches 10-12. */
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                SpareWrite<SocType>(params->EmcBctSpareSecure18, params->EmcBctSpareSecure19);
+                SpareWrite<SocType>(params->EmcBctSpareSecure20, params->EmcBctSpareSecure21);
+                SpareWrite<SocType>(params->EmcBctSpareSecure22, params->EmcBctSpareSecure23);
+            }
+
+            /* Set package and DPD pad control. */
+            reg::Write(PMC + APBDEV_PMC_DDR_CFG, params->PmcDdrCfg);
+
+            /* Start periodic ZQ calibration. */
+            if (params->MemoryType == br::BootMemoryType_LpDdr2 || params->MemoryType == br::BootMemoryType_Ddr3 || params->MemoryType == br::BootMemoryType_LpDdr4) {
+                reg::Write(EMC + EMC_ZCAL_INTERVAL, params->EmcZcalInterval);
+                reg::Write(EMC + EMC_ZCAL_WAIT_CNT, params->EmcZcalWaitCnt);
+                reg::Write(EMC + EMC_ZCAL_MRW_CMD, params->EmcZcalMrwCmd);
+            }
+
+            SpareWrite<SocType>(params->EmcBctSpare12, params->EmcBctSpare13);
+
+            /* Trigger timing update. */
+            reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+
+            if (params->EmcExtraRefreshNum) {
+                reg::Write(EMC + EMC_REF, (params->EmcDevSelect << 30) | (((1 << params->EmcExtraRefreshNum) - 1) << 8) | 3);
+            }
+
+            /* Enable refresh. */
+            reg::Write(EMC + EMC_REFCTRL, params->EmcDevSelect | 0x80000000);
+
+            reg::Write(EMC + EMC_DYN_SELF_REF_CONTROL, params->EmcDynSelfRefControl);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(EMC + EMC_CFG_UPDATE, params->EmcCfgUpdate);
+            }
+
+            reg::Write(EMC + EMC_CFG, params->EmcCfg);
+            reg::Write(EMC + EMC_FDPD_CTRL_DQ, params->EmcFdpdCtrlDq);
+            reg::Write(EMC + EMC_FDPD_CTRL_CMD, params->EmcFdpdCtrlCmd);
+            reg::Write(EMC + EMC_SEL_DPD_CTRL, params->EmcSelDpdCtrl);
+
+            /* Write addr swizzle lock bit. */
+            reg::Write(EMC + EMC_FBIO_SPARE, params->EmcFbioSpare | 2);
+
+            /* Trigger timing update. */
+            reg::Write(EMC + EMC_TIMING_CONTROL, 1);
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(EMC + EMC_CFG_UPDATE, params->EmcCfgUpdate);
+            }
+
+            /* Enable EMC pipe clock gating. */
+            reg::Write(EMC + EMC_CFG_PIPE_CLK, params->EmcCfgPipeClk);
+
+            /* Depending on freqency, enable CMD/CLK fdpd. */
+            reg::Write(EMC + EMC_FDPD_CTRL_CMD_NO_RAMP, params->EmcFdpdCtrlCmdNoRamp);
+
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::ReadWrite(AHB + AHB_ARBITRATION_XBAR_CTRL, AHB_REG_BITS_VALUE(ARBITRATION_XBAR_CTRL_MEM_INIT_DONE, params->AhbArbitrationXbarCtrlMemInitDone));
+            }
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::Write(MC + MC_UNTRANSLATED_REGION_CHECK, params->McUntranslatedRegionCheck);
+            }
+
+            /* Lock carveouts. */
+            reg::Write(MC + MC_VIDEO_PROTECT_REG_CTRL, params->McVideoProtectWriteAccess);
+            reg::Write(MC + MC_SEC_CARVEOUT_REG_CTRL, params->McSecCarveoutProtectWriteAccess);
+            reg::Write(MC + MC_MTS_CARVEOUT_REG_CTRL, params->McMtsCarveoutRegCtrl);
+
+            reg::Write(MC + MC_EMEM_CFG_ACCESS_CTRL, 1);
+
+            if constexpr (SocType == fuse::SocType_Mariko) {
+                reg::ReadWrite(AHB + AHB_ARBITRATION_XBAR_CTRL, AHB_REG_BITS_VALUE(ARBITRATION_XBAR_CTRL_MEM_INIT_DONE, params->AhbArbitrationXbarCtrlMemInitDone));
+            }
+        }
+
+        template<fuse::SocType SocType>
+        void SaveSdramParamsToScratch(BootSdramParams<SocType> *params) {
+            /* TODO */
+        }
+
+        template<fuse::SocType SocType>
+        void InitializeSdram(void *generic_params) {
+            /* Get converted parameters. */
+            auto *sdram_params = static_cast<BootSdramParams<SocType> *>(generic_params);
+
+            /* Enable VDD Memory */
+            pmic::EnableVddMemory(SocType);
+
+            /* Set VDDP select. */
+            reg::Write(PMC + APBDEV_PMC_VDDP_SEL, sdram_params->PmcVddpSel);
+            util::WaitMicroSeconds(sdram_params->PmcVddpSelWait);
+
+            /* If Erista, Set DDR pad voltage. */
+            if constexpr (SocType == fuse::SocType_Erista) {
+                reg::Write(PMC + APBDEV_PMC_DDR_PWR, reg::Read(PMC + APBDEV_PMC_DDR_PWR));
+            }
+
+            /* Turn on MEM IO power. */
+            reg::Write(PMC + APBDEV_PMC_NO_IOPOWER, sdram_params->PmcNoIoPower);
+            reg::Write(PMC + APBDEV_PMC_REG_SHORT, sdram_params->PmcRegShort);
+            reg::Write(PMC + APBDEV_PMC_DDR_CNTRL, sdram_params->PmcDdrCntrl);
+
+            /* Apply patch 1. */
+            *reinterpret_cast<volatile u32 *>(sdram_params->EmcBctSpare0) = sdram_params->EmcBctSpare1;
+
+            /* Do main init. */
+            InitializeSdramImpl<SocType>(sdram_params);
+
+            /* Save parameters to scratch. */
+            SaveSdramParamsToScratch<SocType>(sdram_params);
+        }
+
+    }
+
+    void InitializeSdram() {
+        /* Get soc type. */
+        const auto soc_type = fuse::GetSocType();
+
+        /* Get Sdram params. */
+        void *sdram_params = GetSdramParams(soc_type);
+
+        /* Perform SoC-specific init. */
+        if (soc_type == fuse::SocType_Erista) {
+            InitializeSdram<fuse::SocType_Erista>(sdram_params);
+        } else /* if (soc_type == fuse::SocType_Mariko) */ {
+            InitializeSdram<fuse::SocType_Mariko>(sdram_params);
+        }
+    }
+
+}

fusee_cpp/program/source/fusee_sdram.hpp

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#pragma once
+
+namespace ams::nxboot {
+
+    void InitializeSdram();
+
+}

fusee_cpp/program/source/fusee_uncompress.cpp

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "fusee_uncompress.hpp"
+
+namespace ams::nxboot {
+
+    namespace {
+
+        class Lz4Uncompressor {
+            private:
+                const u8 *src;
+                size_t src_size;
+                size_t src_offset;
+                u8 *dst;
+                size_t dst_size;
+                size_t dst_offset;
+            public:
+                Lz4Uncompressor(void *dst, size_t dst_size, const void *src, size_t src_size) : src(static_cast<const u8 *>(src)), src_size(src_size), src_offset(0), dst(static_cast<u8 *>(dst)), dst_size(dst_size), dst_offset(0) {
+                    /* ... */
+                }
+
+                void Uncompress() {
+                    while (true) {
+                        /* Read a control byte. */
+                        const u8 control = this->ReadByte();
+
+                        /* Copy what it specifies we should copy. */
+                        this->Copy(this->GetCopySize(control >> 4));
+
+                        /* If we've exceeded size, we're done. */
+                        if (this->src_offset >= this->src_size) {
+                            break;
+                        }
+
+                        /* Read the wide copy offset. */
+                        u16 wide_offset = this->ReadByte();
+                        AMS_ABORT_UNLESS(this->CanRead());
+                        wide_offset |= (this->ReadByte() << 8);
+
+                        /* Determine the copy size. */
+                        const size_t wide_copy_size = this->GetCopySize(control & 0xF);
+
+                        /* Copy bytes. */
+                        const size_t end_offset = this->dst_offset + wide_copy_size + 4;
+                        for (size_t cur_offset = this->dst_offset; cur_offset < end_offset; this->dst_offset = (++cur_offset)) {
+                            AMS_ABORT_UNLESS(wide_offset <= cur_offset);
+
+                            this->dst[cur_offset] = this->dst[cur_offset - wide_offset];
+                        }
+                    }
+                }
+            private:
+                u8 ReadByte() {
+                    return this->src[this->src_offset++];
+                }
+
+                bool CanRead() const {
+                    return this->src_offset < this->src_size;
+                }
+
+                size_t GetCopySize(u8 control) {
+                    size_t size = control;
+
+                    if (control >= 0xF) {
+                        do {
+                            AMS_ABORT_UNLESS(this->CanRead());
+                            control = this->ReadByte();
+                            size += control;
+                        } while (control == 0xFF);
+                    }
+
+                    return size;
+                }
+
+                void Copy(size_t size) {
+                    __builtin_memcpy(this->dst + this->dst_offset, this->src + this->src_offset, size);
+                    this->dst_offset += size;
+                    this->src_offset += size;
+                }
+        };
+
+    }
+
+    void Uncompress(void *dst, size_t dst_size, const void *src, size_t src_size) {
+        /* Create an execute a decompressor. */
+        Lz4Uncompressor(dst, dst_size, src, src_size).Uncompress();
+    }
+
+}

fusee_cpp/program/source/fusee_uncompress.hpp

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <vapours.hpp>
+#pragma once
+
+namespace ams::nxboot {
+
+    void Uncompress(void *dst, size_t dst_size, const void *src, size_t src_size);
+
+}

fusee_cpp/program/update_sdram_params.py

@@ -0,0 +1,65 @@
+#!/usr/bin/env python
+import sys, lz4, os
+from struct import unpack as up
+
+def lz4_compress(data):
+    try:
+        import lz4.block as block
+    except ImportError:
+        block = lz4.LZ4_compress
+    return block.compress(data, 'high_compression', store_size=False)
+
+def read_file(fn):
+    with open(fn, 'rb') as f:
+        return f.read()
+
+def write_file(fn, data):
+    with open(fn, 'wb') as f:
+        f.write(data)
+
+def main(argc, argv):
+    if argc != 1:
+        print('Usage: %s' % argv[0])
+        return 1
+    params = {
+        'erista' : {},
+        'mariko' : {},
+    }
+    for fn in os.listdir('sdram_params/bin'):
+        assert fn.startswith('sdram_params_') and fn.endswith('.bin')
+        (_sdram, _params, soc, _id_bin) = tuple(fn.split('_'))
+        param_id = int(_id_bin[:-len('.bin')])
+        assert soc in params.keys()
+        compressed = lz4_compress(read_file(os.path.join('sdram_params/bin', fn)))
+        write_file(os.path.join('sdram_params/lz', fn.replace('.bin', '.lz4')), compressed)
+        params[soc][param_id] = compressed
+    with open('source/fusee_sdram_params.inc', 'w') as f:
+        f.write('%s\n' % "/*")
+        f.write('%s\n' % " * Copyright (c) 2018-2020 Atmosph\xc3re-NX")
+        f.write('%s\n' % " *")
+        f.write('%s\n' % " * This program is free software; you can redistribute it and/or modify it")
+        f.write('%s\n' % " * under the terms and conditions of the GNU General Public License,")
+        f.write('%s\n' % " * version 2, as published by the Free Software Foundation.")
+        f.write('%s\n' % " *")
+        f.write('%s\n' % " * This program is distributed in the hope it will be useful, but WITHOUT")
+        f.write('%s\n' % " * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or")
+        f.write('%s\n' % " * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for")
+        f.write('%s\n' % " * more details.")
+        f.write('%s\n' % " *")
+        f.write('%s\n' % " * You should have received a copy of the GNU General Public License")
+        f.write('%s\n' % " * along with this program.  If not, see <http://www.gnu.org/licenses/>.")
+        f.write('%s\n' % " */")
+        f.write('\n')
+        for soc in ('Erista', 'Mariko'):
+            for param_id in sorted(params[soc.lower()].keys()):
+                compressed = params[soc.lower()][param_id]
+                f.write('%s\n' % ('constexpr inline const u8 SdramParams%s%d[0x%03X] = {' % (soc, param_id, len(compressed))))
+                while compressed:
+                    block = compressed[:0x10]
+                    compressed = compressed[0x10:]
+                    f.write('    %s\n' % (', '.join('0x%02X' % ord(c) for c in block) + ','))
+                f.write('};\n\n')
+    return 0
+
+if __name__ == '__main__':
+    sys.exit(main(len(sys.argv), sys.argv))

libraries/libexosphere/include/exosphere/br/impl/br_common_types.hpp

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::br {
+
+    enum BootMemoryType : u32 {
+        BootMemoryType_None,
+        BootMemoryType_LpDdr2,
+        BootMemoryType_Ddr3,
+        BootMemoryType_LpDdr4,
+    };
+
+}

libraries/libexosphere/include/exosphere/br/impl/br_erista_types.hpp

@@ -15,7 +15,486 @@
  */
 #pragma once
 #include <vapours.hpp>
+#include <exosphere/br/impl/br_common_types.hpp>
 
 namespace ams::br::erista {
 
+    struct BootSdramParams {
+        BootMemoryType MemoryType;
+        u32 PllMInputDivider;
+        u32 PllMFeedbackDivider;
+        u32 PllMStableTime;
+        u32 PllMSetupControl;
+        u32 PllMPostDivider;
+        u32 PllMKCP;
+        u32 PllMKVCO;
+        u32 EmcBctSpare0;
+        u32 EmcBctSpare1;
+        u32 EmcBctSpare2;
+        u32 EmcBctSpare3;
+        u32 EmcBctSpare4;
+        u32 EmcBctSpare5;
+        u32 EmcBctSpare6;
+        u32 EmcBctSpare7;
+        u32 EmcBctSpare8;
+        u32 EmcBctSpare9;
+        u32 EmcBctSpare10;
+        u32 EmcBctSpare11;
+        u32 EmcBctSpare12;
+        u32 EmcBctSpare13;
+        u32 EmcClockSource;
+        u32 EmcClockSourceDll;
+        u32 ClkRstControllerPllmMisc2Override;
+        u32 ClkRstControllerPllmMisc2OverrideEnable;
+        u32 ClearClk2Mc1;
+        u32 EmcAutoCalInterval;
+        u32 EmcAutoCalConfig;
+        u32 EmcAutoCalConfig2;
+        u32 EmcAutoCalConfig3;
+        u32 EmcAutoCalConfig4;
+        u32 EmcAutoCalConfig5;
+        u32 EmcAutoCalConfig6;
+        u32 EmcAutoCalConfig7;
+        u32 EmcAutoCalConfig8;
+        u32 EmcAutoCalVrefSel0;
+        u32 EmcAutoCalVrefSel1;
+        u32 EmcAutoCalChannel;
+        u32 EmcPmacroAutocalCfg0;
+        u32 EmcPmacroAutocalCfg1;
+        u32 EmcPmacroAutocalCfg2;
+        u32 EmcPmacroRxTerm;
+        u32 EmcPmacroDqTxDrv;
+        u32 EmcPmacroCaTxDrv;
+        u32 EmcPmacroCmdTxDrv;
+        u32 EmcPmacroAutocalCfgCommon;
+        u32 EmcPmacroZctrl;
+        u32 EmcAutoCalWait;
+        u32 EmcXm2CompPadCtrl;
+        u32 EmcXm2CompPadCtrl2;
+        u32 EmcXm2CompPadCtrl3;
+        u32 EmcAdrCfg;
+        u32 EmcPinProgramWait;
+        u32 EmcPinExtraWait;
+        u32 EmcPinGpioEn;
+        u32 EmcPinGpio;
+        u32 EmcTimingControlWait;
+        u32 EmcRc;
+        u32 EmcRfc;
+        u32 EmcRfcPb;
+        u32 EmcRefctrl2;
+        u32 EmcRfcSlr;
+        u32 EmcRas;
+        u32 EmcRp;
+        u32 EmcR2r;
+        u32 EmcW2w;
+        u32 EmcR2w;
+        u32 EmcW2r;
+        u32 EmcR2p;
+        u32 EmcW2p;
+        u32 EmcTppd;
+        u32 EmcCcdmw;
+        u32 EmcRdRcd;
+        u32 EmcWrRcd;
+        u32 EmcRrd;
+        u32 EmcRext;
+        u32 EmcWext;
+        u32 EmcWdv;
+        u32 EmcWdvChk;
+        u32 EmcWsv;
+        u32 EmcWev;
+        u32 EmcWdvMask;
+        u32 EmcWsDuration;
+        u32 EmcWeDuration;
+        u32 EmcQUse;
+        u32 EmcQuseWidth;
+        u32 EmcIbdly;
+        u32 EmcObdly;
+        u32 EmcEInput;
+        u32 EmcEInputDuration;
+        u32 EmcPutermExtra;
+        u32 EmcPutermWidth;
+        u32 EmcQRst;
+        u32 EmcQSafe;
+        u32 EmcRdv;
+        u32 EmcRdvMask;
+        u32 EmcRdvEarly;
+        u32 EmcRdvEarlyMask;
+        u32 EmcQpop;
+        u32 EmcRefresh;
+        u32 EmcBurstRefreshNum;
+        u32 EmcPreRefreshReqCnt;
+        u32 EmcPdEx2Wr;
+        u32 EmcPdEx2Rd;
+        u32 EmcPChg2Pden;
+        u32 EmcAct2Pden;
+        u32 EmcAr2Pden;
+        u32 EmcRw2Pden;
+        u32 EmcCke2Pden;
+        u32 EmcPdex2Cke;
+        u32 EmcPdex2Mrr;
+        u32 EmcTxsr;
+        u32 EmcTxsrDll;
+        u32 EmcTcke;
+        u32 EmcTckesr;
+        u32 EmcTpd;
+        u32 EmcTfaw;
+        u32 EmcTrpab;
+        u32 EmcTClkStable;
+        u32 EmcTClkStop;
+        u32 EmcTRefBw;
+        u32 EmcFbioCfg5;
+        u32 EmcFbioCfg7;
+        u32 EmcFbioCfg8;
+        u32 EmcCmdMappingCmd0_0;
+        u32 EmcCmdMappingCmd0_1;
+        u32 EmcCmdMappingCmd0_2;
+        u32 EmcCmdMappingCmd1_0;
+        u32 EmcCmdMappingCmd1_1;
+        u32 EmcCmdMappingCmd1_2;
+        u32 EmcCmdMappingCmd2_0;
+        u32 EmcCmdMappingCmd2_1;
+        u32 EmcCmdMappingCmd2_2;
+        u32 EmcCmdMappingCmd3_0;
+        u32 EmcCmdMappingCmd3_1;
+        u32 EmcCmdMappingCmd3_2;
+        u32 EmcCmdMappingByte;
+        u32 EmcFbioSpare;
+        u32 EmcCfgRsv;
+        u32 EmcMrs;
+        u32 EmcEmrs;
+        u32 EmcEmrs2;
+        u32 EmcEmrs3;
+        u32 EmcMrw1;
+        u32 EmcMrw2;
+        u32 EmcMrw3;
+        u32 EmcMrw4;
+        u32 EmcMrw6;
+        u32 EmcMrw8;
+        u32 EmcMrw9;
+        u32 EmcMrw10;
+        u32 EmcMrw12;
+        u32 EmcMrw13;
+        u32 EmcMrw14;
+        u32 EmcMrwExtra;
+        u32 EmcWarmBootMrwExtra;
+        u32 EmcWarmBootExtraModeRegWriteEnable;
+        u32 EmcExtraModeRegWriteEnable;
+        u32 EmcMrwResetCommand;
+        u32 EmcMrwResetNInitWait;
+        u32 EmcMrsWaitCnt;
+        u32 EmcMrsWaitCnt2;
+        u32 EmcCfg;
+        u32 EmcCfg2;
+        u32 EmcCfgPipe;
+        u32 EmcCfgPipeClk;
+        u32 EmcFdpdCtrlCmdNoRamp;
+        u32 EmcCfgUpdate;
+        u32 EmcDbg;
+        u32 EmcDbgWriteMux;
+        u32 EmcCmdQ;
+        u32 EmcMc2EmcQ;
+        u32 EmcDynSelfRefControl;
+        u32 AhbArbitrationXbarCtrlMemInitDone;
+        u32 EmcCfgDigDll;
+        u32 EmcCfgDigDll_1;
+        u32 EmcCfgDigDllPeriod;
+        u32 EmcDevSelect;
+        u32 EmcSelDpdCtrl;
+        u32 EmcFdpdCtrlDq;
+        u32 EmcFdpdCtrlCmd;
+        u32 EmcPmacroIbVrefDq_0;
+        u32 EmcPmacroIbVrefDq_1;
+        u32 EmcPmacroIbVrefDqs_0;
+        u32 EmcPmacroIbVrefDqs_1;
+        u32 EmcPmacroIbRxrt;
+        u32 EmcCfgPipe1;
+        u32 EmcCfgPipe2;
+        u32 EmcPmacroQuseDdllRank0_0;
+        u32 EmcPmacroQuseDdllRank0_1;
+        u32 EmcPmacroQuseDdllRank0_2;
+        u32 EmcPmacroQuseDdllRank0_3;
+        u32 EmcPmacroQuseDdllRank0_4;
+        u32 EmcPmacroQuseDdllRank0_5;
+        u32 EmcPmacroQuseDdllRank1_0;
+        u32 EmcPmacroQuseDdllRank1_1;
+        u32 EmcPmacroQuseDdllRank1_2;
+        u32 EmcPmacroQuseDdllRank1_3;
+        u32 EmcPmacroQuseDdllRank1_4;
+        u32 EmcPmacroQuseDdllRank1_5;
+        u32 EmcPmacroObDdllLongDqRank0_0;
+        u32 EmcPmacroObDdllLongDqRank0_1;
+        u32 EmcPmacroObDdllLongDqRank0_2;
+        u32 EmcPmacroObDdllLongDqRank0_3;
+        u32 EmcPmacroObDdllLongDqRank0_4;
+        u32 EmcPmacroObDdllLongDqRank0_5;
+        u32 EmcPmacroObDdllLongDqRank1_0;
+        u32 EmcPmacroObDdllLongDqRank1_1;
+        u32 EmcPmacroObDdllLongDqRank1_2;
+        u32 EmcPmacroObDdllLongDqRank1_3;
+        u32 EmcPmacroObDdllLongDqRank1_4;
+        u32 EmcPmacroObDdllLongDqRank1_5;
+        u32 EmcPmacroObDdllLongDqsRank0_0;
+        u32 EmcPmacroObDdllLongDqsRank0_1;
+        u32 EmcPmacroObDdllLongDqsRank0_2;
+        u32 EmcPmacroObDdllLongDqsRank0_3;
+        u32 EmcPmacroObDdllLongDqsRank0_4;
+        u32 EmcPmacroObDdllLongDqsRank0_5;
+        u32 EmcPmacroObDdllLongDqsRank1_0;
+        u32 EmcPmacroObDdllLongDqsRank1_1;
+        u32 EmcPmacroObDdllLongDqsRank1_2;
+        u32 EmcPmacroObDdllLongDqsRank1_3;
+        u32 EmcPmacroObDdllLongDqsRank1_4;
+        u32 EmcPmacroObDdllLongDqsRank1_5;
+        u32 EmcPmacroIbDdllLongDqsRank0_0;
+        u32 EmcPmacroIbDdllLongDqsRank0_1;
+        u32 EmcPmacroIbDdllLongDqsRank0_2;
+        u32 EmcPmacroIbDdllLongDqsRank0_3;
+        u32 EmcPmacroIbDdllLongDqsRank1_0;
+        u32 EmcPmacroIbDdllLongDqsRank1_1;
+        u32 EmcPmacroIbDdllLongDqsRank1_2;
+        u32 EmcPmacroIbDdllLongDqsRank1_3;
+        u32 EmcPmacroDdllLongCmd_0;
+        u32 EmcPmacroDdllLongCmd_1;
+        u32 EmcPmacroDdllLongCmd_2;
+        u32 EmcPmacroDdllLongCmd_3;
+        u32 EmcPmacroDdllLongCmd_4;
+        u32 EmcPmacroDdllShortCmd_0;
+        u32 EmcPmacroDdllShortCmd_1;
+        u32 EmcPmacroDdllShortCmd_2;
+        u32 WarmBootWait;
+        u32 EmcOdtWrite;
+        u32 EmcZcalInterval;
+        u32 EmcZcalWaitCnt;
+        u32 EmcZcalMrwCmd;
+        u32 EmcMrsResetDll;
+        u32 EmcZcalInitDev0;
+        u32 EmcZcalInitDev1;
+        u32 EmcZcalInitWait;
+        u32 EmcZcalWarmColdBootEnables;
+        u32 EmcMrwLpddr2ZcalWarmBoot;
+        u32 EmcZqCalDdr3WarmBoot;
+        u32 EmcZqCalLpDdr4WarmBoot;
+        u32 EmcZcalWarmBootWait;
+        u32 EmcMrsWarmBootEnable;
+        u32 EmcMrsResetDllWait;
+        u32 EmcMrsExtra;
+        u32 EmcWarmBootMrsExtra;
+        u32 EmcEmrsDdr2DllEnable;
+        u32 EmcMrsDdr2DllReset;
+        u32 EmcEmrsDdr2OcdCalib;
+        u32 EmcDdr2Wait;
+        u32 EmcClkenOverride;
+        u32 EmcExtraRefreshNum;
+        u32 EmcClkenOverrideAllWarmBoot;
+        u32 McClkenOverrideAllWarmBoot;
+        u32 EmcCfgDigDllPeriodWarmBoot;
+        u32 PmcVddpSel;
+        u32 PmcVddpSelWait;
+        u32 PmcDdrPwr;
+        u32 PmcDdrCfg;
+        u32 PmcIoDpd3Req;
+        u32 PmcIoDpd3ReqWait;
+        u32 PmcIoDpd4ReqWait;
+        u32 PmcRegShort;
+        u32 PmcNoIoPower;
+        u32 PmcDdrCntrlWait;
+        u32 PmcDdrCntrl;
+        u32 EmcAcpdControl;
+        u32 EmcSwizzleRank0Byte0;
+        u32 EmcSwizzleRank0Byte1;
+        u32 EmcSwizzleRank0Byte2;
+        u32 EmcSwizzleRank0Byte3;
+        u32 EmcSwizzleRank1Byte0;
+        u32 EmcSwizzleRank1Byte1;
+        u32 EmcSwizzleRank1Byte2;
+        u32 EmcSwizzleRank1Byte3;
+        u32 EmcTxdsrvttgen;
+        u32 EmcDataBrlshft0;
+        u32 EmcDataBrlshft1;
+        u32 EmcDqsBrlshft0;
+        u32 EmcDqsBrlshft1;
+        u32 EmcCmdBrlshft0;
+        u32 EmcCmdBrlshft1;
+        u32 EmcCmdBrlshft2;
+        u32 EmcCmdBrlshft3;
+        u32 EmcQuseBrlshft0;
+        u32 EmcQuseBrlshft1;
+        u32 EmcQuseBrlshft2;
+        u32 EmcQuseBrlshft3;
+        u32 EmcDllCfg0;
+        u32 EmcDllCfg1;
+        u32 EmcPmcScratch1;
+        u32 EmcPmcScratch2;
+        u32 EmcPmcScratch3;
+        u32 EmcPmacroPadCfgCtrl;
+        u32 EmcPmacroVttgenCtrl0;
+        u32 EmcPmacroVttgenCtrl1;
+        u32 EmcPmacroVttgenCtrl2;
+        u32 EmcPmacroBrickCtrlRfu1;
+        u32 EmcPmacroCmdBrickCtrlFdpd;
+        u32 EmcPmacroBrickCtrlRfu2;
+        u32 EmcPmacroDataBrickCtrlFdpd;
+        u32 EmcPmacroBgBiasCtrl0;
+        u32 EmcPmacroDataPadRxCtrl;
+        u32 EmcPmacroCmdPadRxCtrl;
+        u32 EmcPmacroDataRxTermMode;
+        u32 EmcPmacroCmdRxTermMode;
+        u32 EmcPmacroDataPadTxCtrl;
+        u32 EmcPmacroCommonPadTxCtrl;
+        u32 EmcPmacroCmdPadTxCtrl;
+        u32 EmcCfg3;
+        u32 EmcPmacroTxPwrd0;
+        u32 EmcPmacroTxPwrd1;
+        u32 EmcPmacroTxPwrd2;
+        u32 EmcPmacroTxPwrd3;
+        u32 EmcPmacroTxPwrd4;
+        u32 EmcPmacroTxPwrd5;
+        u32 EmcConfigSampleDelay;
+        u32 EmcPmacroBrickMapping0;
+        u32 EmcPmacroBrickMapping1;
+        u32 EmcPmacroBrickMapping2;
+        u32 EmcPmacroTxSelClkSrc0;
+        u32 EmcPmacroTxSelClkSrc1;
+        u32 EmcPmacroTxSelClkSrc2;
+        u32 EmcPmacroTxSelClkSrc3;
+        u32 EmcPmacroTxSelClkSrc4;
+        u32 EmcPmacroTxSelClkSrc5;
+        u32 EmcPmacroDdllBypass;
+        u32 EmcPmacroDdllPwrd0;
+        u32 EmcPmacroDdllPwrd1;
+        u32 EmcPmacroDdllPwrd2;
+        u32 EmcPmacroCmdCtrl0;
+        u32 EmcPmacroCmdCtrl1;
+        u32 EmcPmacroCmdCtrl2;
+        u32 McEmemAdrCfg;
+        u32 McEmemAdrCfgDev0;
+        u32 McEmemAdrCfgDev1;
+        u32 McEmemAdrCfgChannelMask;
+        u32 McEmemAdrCfgBankMask0;
+        u32 McEmemAdrCfgBankMask1;
+        u32 McEmemAdrCfgBankMask2;
+        u32 McEmemCfg;
+        u32 McEmemArbCfg;
+        u32 McEmemArbOutstandingReq;
+        u32 McEmemArbRefpbHpCtrl;
+        u32 McEmemArbRefpbBankCtrl;
+        u32 McEmemArbTimingRcd;
+        u32 McEmemArbTimingRp;
+        u32 McEmemArbTimingRc;
+        u32 McEmemArbTimingRas;
+        u32 McEmemArbTimingFaw;
+        u32 McEmemArbTimingRrd;
+        u32 McEmemArbTimingRap2Pre;
+        u32 McEmemArbTimingWap2Pre;
+        u32 McEmemArbTimingR2R;
+        u32 McEmemArbTimingW2W;
+        u32 McEmemArbTimingR2W;
+        u32 McEmemArbTimingW2R;
+        u32 McEmemArbTimingRFCPB;
+        u32 McEmemArbDaTurns;
+        u32 McEmemArbDaCovers;
+        u32 McEmemArbMisc0;
+        u32 McEmemArbMisc1;
+        u32 McEmemArbMisc2;
+        u32 McEmemArbRing1Throttle;
+        u32 McEmemArbOverride;
+        u32 McEmemArbOverride1;
+        u32 McEmemArbRsv;
+        u32 McDaCfg0;
+        u32 McEmemArbTimingCcdmw;
+        u32 McClkenOverride;
+        u32 McStatControl;
+        u32 McVideoProtectBom;
+        u32 McVideoProtectBomAdrHi;
+        u32 McVideoProtectSizeMb;
+        u32 McVideoProtectVprOverride;
+        u32 McVideoProtectVprOverride1;
+        u32 McVideoProtectGpuOverride0;
+        u32 McVideoProtectGpuOverride1;
+        u32 McSecCarveoutBom;
+        u32 McSecCarveoutAdrHi;
+        u32 McSecCarveoutSizeMb;
+        u32 McVideoProtectWriteAccess;
+        u32 McSecCarveoutProtectWriteAccess;
+        u32 McGeneralizedCarveout1Bom;
+        u32 McGeneralizedCarveout1BomHi;
+        u32 McGeneralizedCarveout1Size128kb;
+        u32 McGeneralizedCarveout1Access0;
+        u32 McGeneralizedCarveout1Access1;
+        u32 McGeneralizedCarveout1Access2;
+        u32 McGeneralizedCarveout1Access3;
+        u32 McGeneralizedCarveout1Access4;
+        u32 McGeneralizedCarveout1ForceInternalAccess0;
+        u32 McGeneralizedCarveout1ForceInternalAccess1;
+        u32 McGeneralizedCarveout1ForceInternalAccess2;
+        u32 McGeneralizedCarveout1ForceInternalAccess3;
+        u32 McGeneralizedCarveout1ForceInternalAccess4;
+        u32 McGeneralizedCarveout1Cfg0;
+        u32 McGeneralizedCarveout2Bom;
+        u32 McGeneralizedCarveout2BomHi;
+        u32 McGeneralizedCarveout2Size128kb;
+        u32 McGeneralizedCarveout2Access0;
+        u32 McGeneralizedCarveout2Access1;
+        u32 McGeneralizedCarveout2Access2;
+        u32 McGeneralizedCarveout2Access3;
+        u32 McGeneralizedCarveout2Access4;
+        u32 McGeneralizedCarveout2ForceInternalAccess0;
+        u32 McGeneralizedCarveout2ForceInternalAccess1;
+        u32 McGeneralizedCarveout2ForceInternalAccess2;
+        u32 McGeneralizedCarveout2ForceInternalAccess3;
+        u32 McGeneralizedCarveout2ForceInternalAccess4;
+        u32 McGeneralizedCarveout2Cfg0;
+        u32 McGeneralizedCarveout3Bom;
+        u32 McGeneralizedCarveout3BomHi;
+        u32 McGeneralizedCarveout3Size128kb;
+        u32 McGeneralizedCarveout3Access0;
+        u32 McGeneralizedCarveout3Access1;
+        u32 McGeneralizedCarveout3Access2;
+        u32 McGeneralizedCarveout3Access3;
+        u32 McGeneralizedCarveout3Access4;
+        u32 McGeneralizedCarveout3ForceInternalAccess0;
+        u32 McGeneralizedCarveout3ForceInternalAccess1;
+        u32 McGeneralizedCarveout3ForceInternalAccess2;
+        u32 McGeneralizedCarveout3ForceInternalAccess3;
+        u32 McGeneralizedCarveout3ForceInternalAccess4;
+        u32 McGeneralizedCarveout3Cfg0;
+        u32 McGeneralizedCarveout4Bom;
+        u32 McGeneralizedCarveout4BomHi;
+        u32 McGeneralizedCarveout4Size128kb;
+        u32 McGeneralizedCarveout4Access0;
+        u32 McGeneralizedCarveout4Access1;
+        u32 McGeneralizedCarveout4Access2;
+        u32 McGeneralizedCarveout4Access3;
+        u32 McGeneralizedCarveout4Access4;
+        u32 McGeneralizedCarveout4ForceInternalAccess0;
+        u32 McGeneralizedCarveout4ForceInternalAccess1;
+        u32 McGeneralizedCarveout4ForceInternalAccess2;
+        u32 McGeneralizedCarveout4ForceInternalAccess3;
+        u32 McGeneralizedCarveout4ForceInternalAccess4;
+        u32 McGeneralizedCarveout4Cfg0;
+        u32 McGeneralizedCarveout5Bom;
+        u32 McGeneralizedCarveout5BomHi;
+        u32 McGeneralizedCarveout5Size128kb;
+        u32 McGeneralizedCarveout5Access0;
+        u32 McGeneralizedCarveout5Access1;
+        u32 McGeneralizedCarveout5Access2;
+        u32 McGeneralizedCarveout5Access3;
+        u32 McGeneralizedCarveout5Access4;
+        u32 McGeneralizedCarveout5ForceInternalAccess0;
+        u32 McGeneralizedCarveout5ForceInternalAccess1;
+        u32 McGeneralizedCarveout5ForceInternalAccess2;
+        u32 McGeneralizedCarveout5ForceInternalAccess3;
+        u32 McGeneralizedCarveout5ForceInternalAccess4;
+        u32 McGeneralizedCarveout5Cfg0;
+        u32 EmcCaTrainingEnable;
+        u32 SwizzleRankByteEncode;
+        u32 BootRomPatchControl;
+        u32 BootRomPatchData;
+        u32 McMtsCarveoutBom;
+        u32 McMtsCarveoutAdrHi;
+        u32 McMtsCarveoutSizeMb;
+        u32 McMtsCarveoutRegCtrl;
+    };
+    static_assert(sizeof(BootSdramParams) == 0x768);
+
 }

libraries/libexosphere/include/exosphere/br/impl/br_mariko_types.hpp

@@ -15,7 +15,538 @@
  */
 #pragma once
 #include <vapours.hpp>
+#include <exosphere/br/impl/br_common_types.hpp>
 
 namespace ams::br::mariko {
 
+    struct BootSdramParams {
+        BootMemoryType MemoryType;
+        u32 PllMInputDivider;
+        u32 PllMFeedbackDivider;
+        u32 PllMStableTime;
+        u32 PllMSetupControl;
+        u32 PllMPostDivider;
+        u32 PllMKCP;
+        u32 PllMKVCO;
+        u32 EmcBctSpare0;
+        u32 EmcBctSpare1;
+        u32 EmcBctSpare2;
+        u32 EmcBctSpare3;
+        u32 EmcBctSpare4;
+        u32 EmcBctSpare5;
+        u32 EmcBctSpare6;
+        u32 EmcBctSpare7;
+        u32 EmcBctSpare8;
+        u32 EmcBctSpare9;
+        u32 EmcBctSpare10;
+        u32 EmcBctSpare11;
+        u32 EmcBctSpare12;
+        u32 EmcBctSpare13;
+        u32 EmcBctSpareSecure0;
+        u32 EmcBctSpareSecure1;
+        u32 EmcBctSpareSecure2;
+        u32 EmcBctSpareSecure3;
+        u32 EmcBctSpareSecure4;
+        u32 EmcBctSpareSecure5;
+        u32 EmcBctSpareSecure6;
+        u32 EmcBctSpareSecure7;
+        u32 EmcBctSpareSecure8;
+        u32 EmcBctSpareSecure9;
+        u32 EmcBctSpareSecure10;
+        u32 EmcBctSpareSecure11;
+        u32 EmcBctSpareSecure12;
+        u32 EmcBctSpareSecure13;
+        u32 EmcBctSpareSecure14;
+        u32 EmcBctSpareSecure15;
+        u32 EmcBctSpareSecure16;
+        u32 EmcBctSpareSecure17;
+        u32 EmcBctSpareSecure18;
+        u32 EmcBctSpareSecure19;
+        u32 EmcBctSpareSecure20;
+        u32 EmcBctSpareSecure21;
+        u32 EmcBctSpareSecure22;
+        u32 EmcBctSpareSecure23;
+        u32 EmcClockSource;
+        u32 EmcClockSourceDll;
+        u32 ClkRstControllerPllmMisc2Override;
+        u32 ClkRstControllerPllmMisc2OverrideEnable;
+        u32 ClearClk2Mc1;
+        u32 EmcAutoCalInterval;
+        u32 EmcAutoCalConfig;
+        u32 EmcAutoCalConfig2;
+        u32 EmcAutoCalConfig3;
+        u32 EmcAutoCalConfig4;
+        u32 EmcAutoCalConfig5;
+        u32 EmcAutoCalConfig6;
+        u32 EmcAutoCalConfig7;
+        u32 EmcAutoCalConfig8;
+        u32 EmcAutoCalConfig9;
+        u32 EmcAutoCalVrefSel0;
+        u32 EmcAutoCalVrefSel1;
+        u32 EmcAutoCalChannel;
+        u32 EmcPmacroAutocalCfg0;
+        u32 EmcPmacroAutocalCfg1;
+        u32 EmcPmacroAutocalCfg2;
+        u32 EmcPmacroRxTerm;
+        u32 EmcPmacroDqTxDrv;
+        u32 EmcPmacroCaTxDrv;
+        u32 EmcPmacroCmdTxDrv;
+        u32 EmcPmacroAutocalCfgCommon;
+        u32 EmcPmacroZctrl;
+        u32 EmcAutoCalWait;
+        u32 EmcXm2CompPadCtrl;
+        u32 EmcXm2CompPadCtrl2;
+        u32 EmcXm2CompPadCtrl3;
+        u32 EmcAdrCfg;
+        u32 EmcPinProgramWait;
+        u32 EmcPinExtraWait;
+        u32 EmcPinGpioEn;
+        u32 EmcPinGpio;
+        u32 EmcTimingControlWait;
+        u32 EmcRc;
+        u32 EmcRfc;
+        u32 EmcRfcPb;
+        u32 EmcRefctrl2;
+        u32 EmcRfcSlr;
+        u32 EmcRas;
+        u32 EmcRp;
+        u32 EmcR2r;
+        u32 EmcW2w;
+        u32 EmcR2w;
+        u32 EmcW2r;
+        u32 EmcR2p;
+        u32 EmcW2p;
+        u32 EmcTppd;
+        u32 EmcTrtm;
+        u32 EmcTwtm;
+        u32 EmcTratm;
+        u32 EmcTwatm;
+        u32 EmcTr2ref;
+        u32 EmcCcdmw;
+        u32 EmcRdRcd;
+        u32 EmcWrRcd;
+        u32 EmcRrd;
+        u32 EmcRext;
+        u32 EmcWext;
+        u32 EmcWdv;
+        u32 EmcWdvChk;
+        u32 EmcWsv;
+        u32 EmcWev;
+        u32 EmcWdvMask;
+        u32 EmcWsDuration;
+        u32 EmcWeDuration;
+        u32 EmcQUse;
+        u32 EmcQuseWidth;
+        u32 EmcIbdly;
+        u32 EmcObdly;
+        u32 EmcEInput;
+        u32 EmcEInputDuration;
+        u32 EmcPutermExtra;
+        u32 EmcPutermWidth;
+        u32 EmcQRst;
+        u32 EmcQSafe;
+        u32 EmcRdv;
+        u32 EmcRdvMask;
+        u32 EmcRdvEarly;
+        u32 EmcRdvEarlyMask;
+        u32 EmcQpop;
+        u32 EmcRefresh;
+        u32 EmcBurstRefreshNum;
+        u32 EmcPreRefreshReqCnt;
+        u32 EmcPdEx2Wr;
+        u32 EmcPdEx2Rd;
+        u32 EmcPChg2Pden;
+        u32 EmcAct2Pden;
+        u32 EmcAr2Pden;
+        u32 EmcRw2Pden;
+        u32 EmcCke2Pden;
+        u32 EmcPdex2Cke;
+        u32 EmcPdex2Mrr;
+        u32 EmcTxsr;
+        u32 EmcTxsrDll;
+        u32 EmcTcke;
+        u32 EmcTckesr;
+        u32 EmcTpd;
+        u32 EmcTfaw;
+        u32 EmcTrpab;
+        u32 EmcTClkStable;
+        u32 EmcTClkStop;
+        u32 EmcTRefBw;
+        u32 EmcFbioCfg5;
+        u32 EmcFbioCfg7;
+        u32 EmcFbioCfg8;
+        u32 EmcCmdMappingCmd0_0;
+        u32 EmcCmdMappingCmd0_1;
+        u32 EmcCmdMappingCmd0_2;
+        u32 EmcCmdMappingCmd1_0;
+        u32 EmcCmdMappingCmd1_1;
+        u32 EmcCmdMappingCmd1_2;
+        u32 EmcCmdMappingCmd2_0;
+        u32 EmcCmdMappingCmd2_1;
+        u32 EmcCmdMappingCmd2_2;
+        u32 EmcCmdMappingCmd3_0;
+        u32 EmcCmdMappingCmd3_1;
+        u32 EmcCmdMappingCmd3_2;
+        u32 EmcCmdMappingByte;
+        u32 EmcFbioSpare;
+        u32 EmcCfgRsv;
+        u32 EmcMrs;
+        u32 EmcEmrs;
+        u32 EmcEmrs2;
+        u32 EmcEmrs3;
+        u32 EmcMrw1;
+        u32 EmcMrw2;
+        u32 EmcMrw3;
+        u32 EmcMrw4;
+        u32 EmcMrw6;
+        u32 EmcMrw8;
+        u32 EmcMrw9;
+        u32 EmcMrw10;
+        u32 EmcMrw12;
+        u32 EmcMrw13;
+        u32 EmcMrw14;
+        u32 EmcMrwExtra;
+        u32 EmcWarmBootMrwExtra;
+        u32 EmcWarmBootExtraModeRegWriteEnable;
+        u32 EmcExtraModeRegWriteEnable;
+        u32 EmcMrwResetCommand;
+        u32 EmcMrwResetNInitWait;
+        u32 EmcMrsWaitCnt;
+        u32 EmcMrsWaitCnt2;
+        u32 EmcCfg;
+        u32 EmcCfg2;
+        u32 EmcCfgPipe;
+        u32 EmcCfgPipeClk;
+        u32 EmcFdpdCtrlCmdNoRamp;
+        u32 EmcCfgUpdate;
+        u32 EmcDbg;
+        u32 EmcDbgWriteMux;
+        u32 EmcCmdQ;
+        u32 EmcMc2EmcQ;
+        u32 EmcDynSelfRefControl;
+        u32 AhbArbitrationXbarCtrlMemInitDone;
+        u32 EmcCfgDigDll;
+        u32 EmcCfgDigDll_1;
+        u32 EmcCfgDigDllPeriod;
+        u32 EmcDevSelect;
+        u32 EmcSelDpdCtrl;
+        u32 EmcFdpdCtrlDq;
+        u32 EmcFdpdCtrlCmd;
+        u32 EmcPmacroIbVrefDq_0;
+        u32 EmcPmacroIbVrefDq_1;
+        u32 EmcPmacroIbVrefDqs_0;
+        u32 EmcPmacroIbVrefDqs_1;
+        u32 EmcPmacroIbRxrt;
+        u32 EmcCfgPipe1;
+        u32 EmcCfgPipe2;
+        u32 EmcPmacroQuseDdllRank0_0;
+        u32 EmcPmacroQuseDdllRank0_1;
+        u32 EmcPmacroQuseDdllRank0_2;
+        u32 EmcPmacroQuseDdllRank0_3;
+        u32 EmcPmacroQuseDdllRank0_4;
+        u32 EmcPmacroQuseDdllRank0_5;
+        u32 EmcPmacroQuseDdllRank1_0;
+        u32 EmcPmacroQuseDdllRank1_1;
+        u32 EmcPmacroQuseDdllRank1_2;
+        u32 EmcPmacroQuseDdllRank1_3;
+        u32 EmcPmacroQuseDdllRank1_4;
+        u32 EmcPmacroQuseDdllRank1_5;
+        u32 EmcPmacroObDdllLongDqRank0_0;
+        u32 EmcPmacroObDdllLongDqRank0_1;
+        u32 EmcPmacroObDdllLongDqRank0_2;
+        u32 EmcPmacroObDdllLongDqRank0_3;
+        u32 EmcPmacroObDdllLongDqRank0_4;
+        u32 EmcPmacroObDdllLongDqRank0_5;
+        u32 EmcPmacroObDdllLongDqRank1_0;
+        u32 EmcPmacroObDdllLongDqRank1_1;
+        u32 EmcPmacroObDdllLongDqRank1_2;
+        u32 EmcPmacroObDdllLongDqRank1_3;
+        u32 EmcPmacroObDdllLongDqRank1_4;
+        u32 EmcPmacroObDdllLongDqRank1_5;
+        u32 EmcPmacroObDdllLongDqsRank0_0;
+        u32 EmcPmacroObDdllLongDqsRank0_1;
+        u32 EmcPmacroObDdllLongDqsRank0_2;
+        u32 EmcPmacroObDdllLongDqsRank0_3;
+        u32 EmcPmacroObDdllLongDqsRank0_4;
+        u32 EmcPmacroObDdllLongDqsRank0_5;
+        u32 EmcPmacroObDdllLongDqsRank1_0;
+        u32 EmcPmacroObDdllLongDqsRank1_1;
+        u32 EmcPmacroObDdllLongDqsRank1_2;
+        u32 EmcPmacroObDdllLongDqsRank1_3;
+        u32 EmcPmacroObDdllLongDqsRank1_4;
+        u32 EmcPmacroObDdllLongDqsRank1_5;
+        u32 EmcPmacroIbDdllLongDqsRank0_0;
+        u32 EmcPmacroIbDdllLongDqsRank0_1;
+        u32 EmcPmacroIbDdllLongDqsRank0_2;
+        u32 EmcPmacroIbDdllLongDqsRank0_3;
+        u32 EmcPmacroIbDdllLongDqsRank1_0;
+        u32 EmcPmacroIbDdllLongDqsRank1_1;
+        u32 EmcPmacroIbDdllLongDqsRank1_2;
+        u32 EmcPmacroIbDdllLongDqsRank1_3;
+        u32 EmcPmacroDdllLongCmd_0;
+        u32 EmcPmacroDdllLongCmd_1;
+        u32 EmcPmacroDdllLongCmd_2;
+        u32 EmcPmacroDdllLongCmd_3;
+        u32 EmcPmacroDdllLongCmd_4;
+        u32 EmcPmacroDdllShortCmd_0;
+        u32 EmcPmacroDdllShortCmd_1;
+        u32 EmcPmacroDdllShortCmd_2;
+        u32 EmcPmacroDdllPeriodicOffset;
+        u32 WarmBootWait;
+        u32 EmcOdtWrite;
+        u32 EmcZcalInterval;
+        u32 EmcZcalWaitCnt;
+        u32 EmcZcalMrwCmd;
+        u32 EmcMrsResetDll;
+        u32 EmcZcalInitDev0;
+        u32 EmcZcalInitDev1;
+        u32 EmcZcalInitWait;
+        u32 EmcZcalWarmColdBootEnables;
+        u32 EmcMrwLpddr2ZcalWarmBoot;
+        u32 EmcZqCalDdr3WarmBoot;
+        u32 EmcZqCalLpDdr4WarmBoot;
+        u32 EmcZcalWarmBootWait;
+        u32 EmcMrsWarmBootEnable;
+        u32 EmcMrsResetDllWait;
+        u32 EmcMrsExtra;
+        u32 EmcWarmBootMrsExtra;
+        u32 EmcEmrsDdr2DllEnable;
+        u32 EmcMrsDdr2DllReset;
+        u32 EmcEmrsDdr2OcdCalib;
+        u32 EmcDdr2Wait;
+        u32 EmcClkenOverride;
+        u32 EmcExtraRefreshNum;
+        u32 EmcClkenOverrideAllWarmBoot;
+        u32 McClkenOverrideAllWarmBoot;
+        u32 EmcCfgDigDllPeriodWarmBoot;
+        u32 PmcVddpSel;
+        u32 PmcVddpSelWait;
+        u32 PmcDdrCfg;
+        u32 PmcIoDpd3Req;
+        u32 PmcIoDpd3ReqWait;
+        u32 PmcIoDpd4ReqWait;
+        u32 PmcRegShort;
+        u32 PmcNoIoPower;
+        u32 PmcDdrCntrlWait;
+        u32 PmcDdrCntrl;
+        u32 EmcAcpdControl;
+        u32 EmcSwizzleRank0Byte0;
+        u32 EmcSwizzleRank0Byte1;
+        u32 EmcSwizzleRank0Byte2;
+        u32 EmcSwizzleRank0Byte3;
+        u32 EmcSwizzleRank1Byte0;
+        u32 EmcSwizzleRank1Byte1;
+        u32 EmcSwizzleRank1Byte2;
+        u32 EmcSwizzleRank1Byte3;
+        u32 EmcTxdsrvttgen;
+        u32 EmcDataBrlshft0;
+        u32 EmcDataBrlshft1;
+        u32 EmcDqsBrlshft0;
+        u32 EmcDqsBrlshft1;
+        u32 EmcCmdBrlshft0;
+        u32 EmcCmdBrlshft1;
+        u32 EmcCmdBrlshft2;
+        u32 EmcCmdBrlshft3;
+        u32 EmcQuseBrlshft0;
+        u32 EmcQuseBrlshft1;
+        u32 EmcQuseBrlshft2;
+        u32 EmcQuseBrlshft3;
+        u32 EmcPmacroDllCfg0;
+        u32 EmcPmacroDllCfg1;
+        u32 EmcPmcScratch1;
+        u32 EmcPmcScratch2;
+        u32 EmcPmcScratch3;
+        u32 EmcPmacroPadCfgCtrl;
+        u32 EmcPmacroVttgenCtrl0;
+        u32 EmcPmacroVttgenCtrl1;
+        u32 EmcPmacroVttgenCtrl2;
+        u32 EmcPmacroDsrVttgenCtrl0;
+        u32 EmcPmacroBrickCtrlRfu1;
+        u32 EmcPmacroCmdBrickCtrlFdpd;
+        u32 EmcPmacroBrickCtrlRfu2;
+        u32 EmcPmacroDataBrickCtrlFdpd;
+        u32 EmcPmacroBgBiasCtrl0;
+        u32 EmcPmacroDataPadRxCtrl;
+        u32 EmcPmacroCmdPadRxCtrl;
+        u32 EmcPmacroDataRxTermMode;
+        u32 EmcPmacroCmdRxTermMode;
+        u32 EmcPmacroDataPadTxCtrl;
+        u32 EmcPmacroCmdPadTxCtrl;
+        u32 EmcCfg3;
+        u32 EmcPmacroTxPwrd0;
+        u32 EmcPmacroTxPwrd1;
+        u32 EmcPmacroTxPwrd2;
+        u32 EmcPmacroTxPwrd3;
+        u32 EmcPmacroTxPwrd4;
+        u32 EmcPmacroTxPwrd5;
+        u32 EmcConfigSampleDelay;
+        u32 EmcPmacroBrickMapping0;
+        u32 EmcPmacroBrickMapping1;
+        u32 EmcPmacroBrickMapping2;
+        u32 EmcPmacroTxSelClkSrc0;
+        u32 EmcPmacroTxSelClkSrc1;
+        u32 EmcPmacroTxSelClkSrc2;
+        u32 EmcPmacroTxSelClkSrc3;
+        u32 EmcPmacroTxSelClkSrc4;
+        u32 EmcPmacroTxSelClkSrc5;
+        u32 EmcPmacroPerbitFgcgCtrl0;
+        u32 EmcPmacroPerbitFgcgCtrl1;
+        u32 EmcPmacroPerbitFgcgCtrl2;
+        u32 EmcPmacroPerbitFgcgCtrl3;
+        u32 EmcPmacroPerbitFgcgCtrl4;
+        u32 EmcPmacroPerbitFgcgCtrl5;
+        u32 EmcPmacroPerbitRfuCtrl0;
+        u32 EmcPmacroPerbitRfuCtrl1;
+        u32 EmcPmacroPerbitRfuCtrl2;
+        u32 EmcPmacroPerbitRfuCtrl3;
+        u32 EmcPmacroPerbitRfuCtrl4;
+        u32 EmcPmacroPerbitRfuCtrl5;
+        u32 EmcPmacroPerbitRfu1Ctrl0;
+        u32 EmcPmacroPerbitRfu1Ctrl1;
+        u32 EmcPmacroPerbitRfu1Ctrl2;
+        u32 EmcPmacroPerbitRfu1Ctrl3;
+        u32 EmcPmacroPerbitRfu1Ctrl4;
+        u32 EmcPmacroPerbitRfu1Ctrl5;
+        u32 EmcPmacroDataPiCtrl;
+        u32 EmcPmacroCmdPiCtrl;
+        u32 EmcPmacroDdllBypass;
+        u32 EmcPmacroDdllPwrd0;
+        u32 EmcPmacroDdllPwrd1;
+        u32 EmcPmacroDdllPwrd2;
+        u32 EmcPmacroCmdCtrl0;
+        u32 EmcPmacroCmdCtrl1;
+        u32 EmcPmacroCmdCtrl2;
+        u32 McEmemAdrCfg;
+        u32 McEmemAdrCfgDev0;
+        u32 McEmemAdrCfgDev1;
+        u32 McEmemAdrCfgChannelMask;
+        u32 McEmemAdrCfgBankMask0;
+        u32 McEmemAdrCfgBankMask1;
+        u32 McEmemAdrCfgBankMask2;
+        u32 McEmemCfg;
+        u32 McEmemArbCfg;
+        u32 McEmemArbOutstandingReq;
+        u32 McEmemArbRefpbHpCtrl;
+        u32 McEmemArbRefpbBankCtrl;
+        u32 McEmemArbTimingRcd;
+        u32 McEmemArbTimingRp;
+        u32 McEmemArbTimingRc;
+        u32 McEmemArbTimingRas;
+        u32 McEmemArbTimingFaw;
+        u32 McEmemArbTimingRrd;
+        u32 McEmemArbTimingRap2Pre;
+        u32 McEmemArbTimingWap2Pre;
+        u32 McEmemArbTimingR2R;
+        u32 McEmemArbTimingW2W;
+        u32 McEmemArbTimingR2W;
+        u32 McEmemArbTimingW2R;
+        u32 McEmemArbTimingRFCPB;
+        u32 McEmemArbDaTurns;
+        u32 McEmemArbDaCovers;
+        u32 McEmemArbMisc0;
+        u32 McEmemArbMisc1;
+        u32 McEmemArbMisc2;
+        u32 McEmemArbRing1Throttle;
+        u32 McEmemArbOverride;
+        u32 McEmemArbOverride1;
+        u32 McEmemArbRsv;
+        u32 McDaCfg0;
+        u32 McEmemArbTimingCcdmw;
+        u32 McClkenOverride;
+        u32 McStatControl;
+        u32 McVideoProtectBom;
+        u32 McVideoProtectBomAdrHi;
+        u32 McVideoProtectSizeMb;
+        u32 McVideoProtectVprOverride;
+        u32 McVideoProtectVprOverride1;
+        u32 McVideoProtectGpuOverride0;
+        u32 McVideoProtectGpuOverride1;
+        u32 McSecCarveoutBom;
+        u32 McSecCarveoutAdrHi;
+        u32 McSecCarveoutSizeMb;
+        u32 McVideoProtectWriteAccess;
+        u32 McSecCarveoutProtectWriteAccess;
+        u32 McGeneralizedCarveout1Bom;
+        u32 McGeneralizedCarveout1BomHi;
+        u32 McGeneralizedCarveout1Size128kb;
+        u32 McGeneralizedCarveout1Access0;
+        u32 McGeneralizedCarveout1Access1;
+        u32 McGeneralizedCarveout1Access2;
+        u32 McGeneralizedCarveout1Access3;
+        u32 McGeneralizedCarveout1Access4;
+        u32 McGeneralizedCarveout1ForceInternalAccess0;
+        u32 McGeneralizedCarveout1ForceInternalAccess1;
+        u32 McGeneralizedCarveout1ForceInternalAccess2;
+        u32 McGeneralizedCarveout1ForceInternalAccess3;
+        u32 McGeneralizedCarveout1ForceInternalAccess4;
+        u32 McGeneralizedCarveout1Cfg0;
+        u32 McGeneralizedCarveout2Bom;
+        u32 McGeneralizedCarveout2BomHi;
+        u32 McGeneralizedCarveout2Size128kb;
+        u32 McGeneralizedCarveout2Access0;
+        u32 McGeneralizedCarveout2Access1;
+        u32 McGeneralizedCarveout2Access2;
+        u32 McGeneralizedCarveout2Access3;
+        u32 McGeneralizedCarveout2Access4;
+        u32 McGeneralizedCarveout2ForceInternalAccess0;
+        u32 McGeneralizedCarveout2ForceInternalAccess1;
+        u32 McGeneralizedCarveout2ForceInternalAccess2;
+        u32 McGeneralizedCarveout2ForceInternalAccess3;
+        u32 McGeneralizedCarveout2ForceInternalAccess4;
+        u32 McGeneralizedCarveout2Cfg0;
+        u32 McGeneralizedCarveout3Bom;
+        u32 McGeneralizedCarveout3BomHi;
+        u32 McGeneralizedCarveout3Size128kb;
+        u32 McGeneralizedCarveout3Access0;
+        u32 McGeneralizedCarveout3Access1;
+        u32 McGeneralizedCarveout3Access2;
+        u32 McGeneralizedCarveout3Access3;
+        u32 McGeneralizedCarveout3Access4;
+        u32 McGeneralizedCarveout3ForceInternalAccess0;
+        u32 McGeneralizedCarveout3ForceInternalAccess1;
+        u32 McGeneralizedCarveout3ForceInternalAccess2;
+        u32 McGeneralizedCarveout3ForceInternalAccess3;
+        u32 McGeneralizedCarveout3ForceInternalAccess4;
+        u32 McGeneralizedCarveout3Cfg0;
+        u32 McGeneralizedCarveout4Bom;
+        u32 McGeneralizedCarveout4BomHi;
+        u32 McGeneralizedCarveout4Size128kb;
+        u32 McGeneralizedCarveout4Access0;
+        u32 McGeneralizedCarveout4Access1;
+        u32 McGeneralizedCarveout4Access2;
+        u32 McGeneralizedCarveout4Access3;
+        u32 McGeneralizedCarveout4Access4;
+        u32 McGeneralizedCarveout4ForceInternalAccess0;
+        u32 McGeneralizedCarveout4ForceInternalAccess1;
+        u32 McGeneralizedCarveout4ForceInternalAccess2;
+        u32 McGeneralizedCarveout4ForceInternalAccess3;
+        u32 McGeneralizedCarveout4ForceInternalAccess4;
+        u32 McGeneralizedCarveout4Cfg0;
+        u32 McGeneralizedCarveout5Bom;
+        u32 McGeneralizedCarveout5BomHi;
+        u32 McGeneralizedCarveout5Size128kb;
+        u32 McGeneralizedCarveout5Access0;
+        u32 McGeneralizedCarveout5Access1;
+        u32 McGeneralizedCarveout5Access2;
+        u32 McGeneralizedCarveout5Access3;
+        u32 McGeneralizedCarveout5Access4;
+        u32 McGeneralizedCarveout5ForceInternalAccess0;
+        u32 McGeneralizedCarveout5ForceInternalAccess1;
+        u32 McGeneralizedCarveout5ForceInternalAccess2;
+        u32 McGeneralizedCarveout5ForceInternalAccess3;
+        u32 McGeneralizedCarveout5ForceInternalAccess4;
+        u32 McGeneralizedCarveout5Cfg0;
+        u32 EmcCaTrainingEnable;
+        u32 SwizzleRankByteEncode;
+        u32 BootRomPatchControl;
+        u32 BootRomPatchData;
+        u32 McMtsCarveoutBom;
+        u32 McMtsCarveoutAdrHi;
+        u32 McMtsCarveoutSizeMb;
+        u32 McMtsCarveoutRegCtrl;
+        u32 McUntranslatedRegionCheck;
+        u32 BCT_NA;
+    };
+    static_assert(sizeof(BootSdramParams) == 0x838);
+
 }

libraries/libexosphere/include/exosphere/pmic_setup.hpp

@@ -24,4 +24,6 @@ namespace ams::pmic {
     void EnableVddCore(fuse::SocType soc_type);
     void EnableLdo8();
 
+    void EnableVddMemory(fuse::SocType soc_type);
+
 }

libraries/libexosphere/source/libc/libgcc_thumb_case.arch.arm.s

@@ -52,3 +52,23 @@ __gnu_thumb1_case_uhi:
     bx  lr
 .type __gnu_thumb1_case_uhi, %function
 .size __gnu_thumb1_case_uhi, .-__gnu_thumb1_case_uhi
+
+.section    .text.__gnu_thumb1_case_si, "ax", %progbits
+.globl __gnu_thumb1_case_si
+.align      0
+.thumb_func
+.syntax unified
+__gnu_thumb1_case_si:
+    push    {r0, r1}
+    mov     r1, lr
+    adds.n  r1, r1, #2
+    lsrs    r1, r1, #2
+    lsls    r0, r0, #2
+    lsls    r1, r1, #2
+    ldr     r0, [r1, r0]
+    adds    r0, r0, r1
+    mov     lr, r0
+    pop     {r0, r1}
+    bx      lr
+.type __gnu_thumb1_case_si, %function
+.size __gnu_thumb1_case_si, .-__gnu_thumb1_case_si

libraries/libexosphere/source/pmic/pmic_api.cpp

@@ -35,6 +35,8 @@ namespace ams::pmic {
         constexpr inline int Max77620RegisterCnfgBbc    = 0x04;
         constexpr inline int Max77620RegisterOnOffStat  = 0x15;
         constexpr inline int Max77620RegisterSd0        = 0x16;
+        constexpr inline int Max77620RegisterSd1        = 0x17;
+        constexpr inline int Max77620RegisterCnfg2Sd    = 0x22;
         constexpr inline int Max77620RegisterCnfg1Ldo8  = 0x33;
         constexpr inline int Max77620RegisterGpio0      = 0x36;
         constexpr inline int Max77620RegisterAmeGpio    = 0x40;
@@ -276,4 +278,14 @@ namespace ams::pmic {
         i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfg1Ldo8, 0xE8);
     }
 
+    void EnableVddMemory(fuse::SocType soc_type) {
+        /* Disable remote sense for Sd1. */
+        i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfg2Sd, 0x05);
+
+        /* On Erista, set Sd1 voltage. */
+        if (soc_type == fuse::SocType_Erista) {
+            SetVoltage(Max77620RegisterSd1, 1100);
+        }
+    }
+
 }

libraries/libvapours/include/vapours/tegra/tegra_ahb_arbc.hpp

@@ -28,6 +28,7 @@
 #define AHB_MASTER_SWID               (0x018)
 #define AHB_MASTER_SWID_1             (0x038)
 #define AHB_GIZMO_TZRAM               (0x054)
+#define AHB_ARBITRATION_XBAR_CTRL     (0x0E0)
 #define AHB_AHB_SPARE_REG             (0x110)
 
 #define AHB_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (AHB_, NAME)
@@ -46,6 +47,8 @@ DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA,  5, ENABLE, DISABLE);
 DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB,     6, ENABLE, DISABLE);
 DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2,   18, ENABLE, DISABLE);
 
+DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_XBAR_CTRL_MEM_INIT_DONE, 16, NOT_DONE, DONE);
+
 DEFINE_AHB_REG(AHB_SPARE_REG_CSITE_PADMACRO3_TRIM_SEL, 0, 5);
 DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_OBS_OVERRIDE_EN, 5, DISABLE, ENABLE);
 DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_APB2JTAG_OVERRIDE_EN, 6, DISABLE, ENABLE);

libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp

@@ -41,6 +41,9 @@
 #define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE       (0x030)
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB          (0x048)
 #define CLK_RST_CONTROLLER_OSC_CTRL              (0x050)
+#define CLK_RST_CONTROLLER_PLLM_BASE             (0x090)
+#define CLK_RST_CONTROLLER_PLLM_MISC1            (0x098)
+#define CLK_RST_CONTROLLER_PLLM_MISC2            (0x09C)
 #define CLK_RST_CONTROLLER_PLLD_BASE             (0x0D0)
 #define CLK_RST_CONTROLLER_PLLD_MISC1            (0x0D8)
 #define CLK_RST_CONTROLLER_PLLD_MISC             (0x0DC)
@@ -92,6 +95,14 @@ DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
 DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
 DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(OSC_CTRL_OSC_FREQ, 28, OSC13, OSC16P8, RSVD2, RSVD3, OSC19P2, OSC38P4, RSVD6, RSVD7, OSC12, OSC48, RSVD10, RSVD11, OSC26, RSVD13, RSVD14, RSVD15);
 
+DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
+DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
+DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_LOCK, 27, NOT_LOCK, LOCK);
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_BYPASSPLL, 31, DISABLE, ENABLE);
+
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC,  23, BRICK, PLL_D);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE,  30, DISABLE, ENABLE);
@@ -171,6 +182,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
 #define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF          (0x62C)
 #define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC          (0x630)
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6              (0x65C)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL           (0x664)
 #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C)
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM   (0x694)
 #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC             (0x6A4)

libraries/libvapours/include/vapours/tegra/tegra_emc.hpp

@@ -25,23 +25,521 @@
 #define EMC0_ADDRESS(x) (0x7001E000 + x)
 #define EMC1_ADDRESS(x) (0x7001F000 + x)
 
-#define EMC_CFG                    (0x00C)
-#define EMC_ADR_CFG                (0x010)
-#define EMC_TIMING_CONTROL         (0x028)
-#define EMC_SELF_REF               (0x0E0)
-#define EMC_MRW                    (0x0E8)
-#define EMC_FBIO_CFG5              (0x104)
-#define EMC_MRW3                   (0x138)
-#define EMC_AUTO_CAL_CONFIG        (0x2A4)
-#define EMC_REQ_CTRL               (0x2B0)
-#define EMC_EMC_STATUS             (0x2B4)
-#define EMC_CFG_DIG_DLL            (0x2BC)
-#define EMC_ZCAL_INTERVAL          (0x2E0)
-#define EMC_PMC_SCRATCH3           (0x448)
-#define EMC_FBIO_CFG7              (0x584)
-#define EMC_PMACRO_CFG_PM_GLOBAL_0 (0xC30)
-#define EMC_PMACRO_TRAINING_CTRL_0 (0xCF8)
-#define EMC_PMACRO_TRAINING_CTRL_1 (0xCFC)
+#define EMC_INTSTATUS                             (0x000)
+#define EMC_DBG                                   (0x008)
+#define EMC_CFG                                   (0x00C)
+#define EMC_ADR_CFG                               (0x010)
+#define EMC_REFCTRL                               (0x020)
+#define EMC_PIN                                   (0x024)
+#define EMC_TIMING_CONTROL                        (0x028)
+#define EMC_RC                                    (0x02C)
+#define EMC_RFC                                   (0x030)
+#define EMC_RAS                                   (0x034)
+#define EMC_RP                                    (0x038)
+#define EMC_R2W                                   (0x03C)
+#define EMC_W2R                                   (0x040)
+#define EMC_R2P                                   (0x044)
+#define EMC_W2P                                   (0x048)
+#define EMC_RD_RCD                                (0x04C)
+#define EMC_WR_RCD                                (0x050)
+#define EMC_RRD                                   (0x054)
+#define EMC_REXT                                  (0x058)
+#define EMC_WDV                                   (0x05C)
+#define EMC_QUSE                                  (0x060)
+#define EMC_QRST                                  (0x064)
+#define EMC_QSAFE                                 (0x068)
+#define EMC_RDV                                   (0x06C)
+#define EMC_REFRESH                               (0x070)
+#define EMC_BURST_REFRESH_NUM                     (0x074)
+#define EMC_PDEX2WR                               (0x078)
+#define EMC_PDEX2RD                               (0x07C)
+#define EMC_PCHG2PDEN                             (0x080)
+#define EMC_ACT2PDEN                              (0x084)
+#define EMC_AR2PDEN                               (0x088)
+#define EMC_RW2PDEN                               (0x08C)
+#define EMC_TXSR                                  (0x090)
+#define EMC_TCKE                                  (0x094)
+#define EMC_TFAW                                  (0x098)
+#define EMC_TRPAB                                 (0x09C)
+#define EMC_TCLKSTABLE                            (0x0A0)
+#define EMC_TCLKSTOP                              (0x0A4)
+#define EMC_TREFBW                                (0x0A8)
+#define EMC_TPPD                                  (0x0AC)
+#define EMC_ODT_WRITE                             (0x0B0)
+#define EMC_PDEX2MRR                              (0x0B4)
+#define EMC_WEXT                                  (0x0B8)
+#define EMC_TRTM                                  (0x0BC)
+#define EMC_RFC_SLR                               (0x0C0)
+#define EMC_MRS_WAIT_CNT2                         (0x0C4)
+#define EMC_MRS_WAIT_CNT                          (0x0C8)
+#define EMC_MRS                                   (0x0CC)
+#define EMC_EMRS                                  (0x0D0)
+#define EMC_REF                                   (0x0D4)
+#define EMC_NOP                                   (0x0DC)
+#define EMC_SELF_REF                              (0x0E0)
+#define EMC_MRW                                   (0x0E8)
+#define EMC_MRR                                   (0x0EC)
+#define EMC_CMDQ                                  (0x0F0)
+#define EMC_MC2EMCQ                               (0x0F4)
+#define EMC_TWTM                                  (0x0F8)
+#define EMC_TRATM                                 (0x0FC)
+#define EMC_FBIO_SPARE                            (0x100)
+#define EMC_FBIO_CFG5                             (0x104)
+#define EMC_TWATM                                 (0x108)
+#define EMC_TR2REF                                (0x10C)
+#define EMC_PMACRO_DATA_PI_CTRL                   (0x110)
+#define EMC_PMACRO_CMD_PI_CTRL                    (0x114)
+#define EMC_PDEX2CKE                              (0x118)
+#define EMC_CKE2PDEN                              (0x11C)
+#define EMC_CFG_RSV                               (0x120)
+#define EMC_ACPD_CONTROL                          (0x124)
+#define EMC_MPC                                   (0x128)
+#define EMC_EMRS2                                 (0x12C)
+#define EMC_MRW2                                  (0x134)
+#define EMC_MRW3                                  (0x138)
+#define EMC_MRW3                                  (0x138)
+#define EMC_MRW4                                  (0x13C)
+#define EMC_CLKEN_OVERRIDE                        (0x140)
+#define EMC_R2R                                   (0x144)
+#define EMC_W2W                                   (0x148)
+#define EMC_EINPUT                                (0x14C)
+#define EMC_EINPUT_DURATION                       (0x150)
+#define EMC_PUTERM_EXTRA                          (0x154)
+#define EMC_TCKESR                                (0x158)
+#define EMC_TPD                                   (0x15C)
+#define EMC_AUTO_CAL_CONFIG                       (0x2A4)
+#define EMC_AUTO_CAL_INTERVAL                     (0x2A8)
+#define EMC_REQ_CTRL                              (0x2B0)
+#define EMC_EMC_STATUS                            (0x2B4)
+#define EMC_CFG_2                                 (0x2B8)
+#define EMC_CFG_DIG_DLL                           (0x2BC)
+#define EMC_CFG_DIG_DLL_PERIOD                    (0x2C0)
+#define EMC_DIG_DLL_STATUS                        (0x2C4)
+#define EMC_CFG_DIG_DLL_1                         (0x2C8)
+#define EMC_RDV_MASK                              (0x2CC)
+#define EMC_WDV_MASK                              (0x2D0)
+#define EMC_RDV_EARLY_MASK                        (0x2D4)
+#define EMC_RDV_EARLY                             (0x2D8)
+#define EMC_AUTO_CAL_CONFIG8                      (0x2DC)
+#define EMC_ZCAL_INTERVAL                         (0x2E0)
+#define EMC_ZCAL_WAIT_CNT                         (0x2E4)
+#define EMC_ZCAL_MRW_CMD                          (0x2E8)
+#define EMC_ZQ_CAL                                (0x2EC)
+#define EMC_XM2COMPPADCTRL3                       (0x2F4)
+#define EMC_AUTO_CAL_VREF_SEL_0                   (0x2F8)
+#define EMC_AUTO_CAL_VREF_SEL_1                   (0x300)
+#define EMC_XM2COMPPADCTRL                        (0x30C)
+#define EMC_FDPD_CTRL_DQ                          (0x310)
+#define EMC_FDPD_CTRL_CMD                         (0x314)
+#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD            (0x318)
+#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD           (0x31C)
+#define EMC_SCRATCH0                              (0x324)
+#define EMC_PMACRO_BRICK_CTRL_RFU1                (0x330)
+#define EMC_PMACRO_BRICK_CTRL_RFU2                (0x334)
+#define EMC_CMD_MAPPING_CMD0_0                    (0x380)
+#define EMC_CMD_MAPPING_CMD0_1                    (0x384)
+#define EMC_CMD_MAPPING_CMD0_2                    (0x388)
+#define EMC_CMD_MAPPING_CMD1_0                    (0x38C)
+#define EMC_CMD_MAPPING_CMD1_1                    (0x390)
+#define EMC_CMD_MAPPING_CMD1_2                    (0x394)
+#define EMC_CMD_MAPPING_CMD2_0                    (0x398)
+#define EMC_CMD_MAPPING_CMD2_1                    (0x39C)
+#define EMC_CMD_MAPPING_CMD2_2                    (0x3A0)
+#define EMC_CMD_MAPPING_CMD3_0                    (0x3A4)
+#define EMC_CMD_MAPPING_CMD3_1                    (0x3A8)
+#define EMC_CMD_MAPPING_CMD3_2                    (0x3AC)
+#define EMC_CMD_MAPPING_BYTE                      (0x3B0)
+#define EMC_TR_TIMING_0                           (0x3B4)
+#define EMC_TR_CTRL_0                             (0x3B8)
+#define EMC_TR_CTRL_1                             (0x3BC)
+#define EMC_SWITCH_BACK_CTRL                      (0x3C0)
+#define EMC_TR_RDV                                (0x3C4)
+#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE        (0x3CC)
+#define EMC_SEL_DPD_CTRL                          (0x3D8)
+#define EMC_PRE_REFRESH_REQ_CNT                   (0x3DC)
+#define EMC_DYN_SELF_REF_CONTROL                  (0x3E0)
+#define EMC_TXSRDLL                               (0x3E4)
+#define EMC_CCFIFO_ADDR                           (0x3E8)
+#define EMC_CCFIFO_DATA                           (0x3EC)
+#define EMC_CCFIFO_STATUS                         (0x3F0)
+#define EMC_TR_QPOP                               (0x3F4)
+#define EMC_TR_RDV_MASK                           (0x3F8)
+#define EMC_TR_QSAFE                              (0x3FC)
+#define EMC_TR_QRST                               (0x400)
+#define EMC_SWIZZLE_RANK0_BYTE0                   (0x404)
+#define EMC_SWIZZLE_RANK0_BYTE1                   (0x408)
+#define EMC_SWIZZLE_RANK0_BYTE2                   (0x40C)
+#define EMC_SWIZZLE_RANK0_BYTE3                   (0x410)
+#define EMC_SWIZZLE_RANK1_BYTE0                   (0x418)
+#define EMC_SWIZZLE_RANK1_BYTE1                   (0x41C)
+#define EMC_SWIZZLE_RANK1_BYTE2                   (0x420)
+#define EMC_SWIZZLE_RANK1_BYTE3                   (0x424)
+#define EMC_ISSUE_QRST                            (0x428)
+#define EMC_AUTO_CAL_CONFIG9                      (0x42C)
+#define EMC_PMC_SCRATCH1                          (0x440)
+#define EMC_PMC_SCRATCH2                          (0x444)
+#define EMC_PMC_SCRATCH3                          (0x448)
+#define EMC_AUTO_CAL_CONFIG2                      (0x458)
+#define EMC_AUTO_CAL_CONFIG3                      (0x45C)
+#define EMC_TR_DVFS                               (0x460)
+#define EMC_AUTO_CAL_CHANNEL                      (0x464)
+#define EMC_IBDLY                                 (0x468)
+#define EMC_OBDLY                                 (0x46C)
+#define EMC_TXDSRVTTGEN                           (0x480)
+#define EMC_WE_DURATION                           (0x48C)
+#define EMC_WS_DURATION                           (0x490)
+#define EMC_WEV                                   (0x494)
+#define EMC_WSV                                   (0x498)
+#define EMC_CFG_3                                 (0x49C)
+#define EMC_MRW5                                  (0x4A0)
+#define EMC_MRW6                                  (0x4A4)
+#define EMC_MRW7                                  (0x4A8)
+#define EMC_MRW8                                  (0x4AC)
+#define EMC_MRW9                                  (0x4B0)
+#define EMC_MRW10                                 (0x4B4)
+#define EMC_MRW11                                 (0x4B8)
+#define EMC_MRW12                                 (0x4BC)
+#define EMC_MRW13                                 (0x4C0)
+#define EMC_MRW14                                 (0x4C4)
+#define EMC_MRW15                                 (0x4D0)
+#define EMC_CFG_SYNC                              (0x4D4)
+#define EMC_FDPD_CTRL_CMD_NO_RAMP                 (0x4D8)
+#define EMC_WDV_CHK                               (0x4E0)
+#define EMC_CFG_PIPE_2                            (0x554)
+#define EMC_CFG_PIPE_CLK                          (0x558)
+#define EMC_CFG_PIPE_1                            (0x55C)
+#define EMC_CFG_PIPE                              (0x560)
+#define EMC_QPOP                                  (0x564)
+#define EMC_QUSE_WIDTH                            (0x568)
+#define EMC_PUTERM_WIDTH                          (0x56C)
+#define EMC_AUTO_CAL_CONFIG7                      (0x574)
+#define EMC_XM2COMPPADCTRL2                       (0x578)
+#define EMC_REFCTRL2                              (0x580)
+#define EMC_FBIO_CFG7                             (0x584)
+#define EMC_DATA_BRLSHFT_0                        (0x588)
+#define EMC_DATA_BRLSHFT_1                        (0x58C)
+#define EMC_RFCPB                                 (0x590)
+#define EMC_DQS_BRLSHFT_0                         (0x594)
+#define EMC_DQS_BRLSHFT_1                         (0x598)
+#define EMC_CMD_BRLSHFT_0                         (0x59C)
+#define EMC_CMD_BRLSHFT_1                         (0x5A0)
+#define EMC_CMD_BRLSHFT_2                         (0x5A4)
+#define EMC_CMD_BRLSHFT_3                         (0x5A8)
+#define EMC_QUSE_BRLSHFT_0                        (0x5AC)
+#define EMC_AUTO_CAL_CONFIG4                      (0x5B0)
+#define EMC_AUTO_CAL_CONFIG5                      (0x5B4)
+#define EMC_QUSE_BRLSHFT_1                        (0x5B8)
+#define EMC_QUSE_BRLSHFT_2                        (0x5BC)
+#define EMC_CCDMW                                 (0x5C0)
+#define EMC_QUSE_BRLSHFT_3                        (0x5C4)
+#define EMC_FBIO_CFG8                             (0x5C8)
+#define EMC_AUTO_CAL_CONFIG6                      (0x5CC)
+
+/* Erista */
+#define EMC_DLL_CFG_0                             (0x5E4)
+#define EMC_DLL_CFG_1                             (0x5E8)
+
+/* Mariko */
+#define EMC_PMACRO_DLL_CFG_0                      (0x5E4)
+#define EMC_PMACRO_DLL_CFG_1                      (0x5E8)
+
+#define EMC_CONFIG_SAMPLE_DELAY                   (0x5F0)
+#define EMC_CFG_UPDATE                            (0x5F4)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_0              (0x600)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_1              (0x604)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_2              (0x608)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_3              (0x60C)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_4              (0x610)
+#define EMC_PMACRO_QUSE_DDLL_RANK0_5              (0x614)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_4              (0x630)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_5              (0x634)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_0              (0x620)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_1              (0x624)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_2              (0x628)
+#define EMC_PMACRO_QUSE_DDLL_RANK1_3              (0x62C)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0        (0x640)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1        (0x644)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2        (0x648)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3        (0x64C)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4        (0x650)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5        (0x654)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0        (0x660)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1        (0x664)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2        (0x668)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3        (0x66C)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4        (0x670)
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5        (0x674)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0       (0x680)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1       (0x684)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2       (0x688)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3       (0x68C)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4       (0x690)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5       (0x694)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0       (0x6A0)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1       (0x6A4)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2       (0x6A8)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3       (0x6AC)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4       (0x6B0)
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5       (0x6B4)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0       (0x6C0)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1       (0x6C4)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2       (0x6C8)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3       (0x6CC)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0       (0x6E0)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1       (0x6E4)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2       (0x6E8)
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3       (0x6EC)
+#define EMC_PMACRO_AUTOCAL_CFG_0                  (0x700)
+#define EMC_PMACRO_AUTOCAL_CFG_1                  (0x704)
+#define EMC_PMACRO_AUTOCAL_CFG_2                  (0x708)
+#define EMC_PMACRO_TX_PWRD_0                      (0x720)
+#define EMC_PMACRO_TX_PWRD_1                      (0x724)
+#define EMC_PMACRO_TX_PWRD_2                      (0x728)
+#define EMC_PMACRO_TX_PWRD_3                      (0x72C)
+#define EMC_PMACRO_TX_PWRD_4                      (0x730)
+#define EMC_PMACRO_TX_PWRD_5                      (0x734)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_0               (0x740)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_1               (0x744)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_3               (0x74C)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_2               (0x748)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_4               (0x750)
+#define EMC_PMACRO_TX_SEL_CLK_SRC_5               (0x754)
+#define EMC_PMACRO_DDLL_BYPASS                    (0x760)
+#define EMC_PMACRO_DDLL_PWRD_0                    (0x770)
+#define EMC_PMACRO_DDLL_PWRD_1                    (0x774)
+#define EMC_PMACRO_DDLL_PWRD_2                    (0x778)
+#define EMC_PMACRO_CMD_CTRL_0                     (0x780)
+#define EMC_PMACRO_CMD_CTRL_1                     (0x784)
+#define EMC_PMACRO_CMD_CTRL_2                     (0x788)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 (0x800)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 (0x804)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 (0x808)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 (0x80C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 (0x810)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 (0x814)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 (0x818)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 (0x81C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 (0x820)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 (0x824)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 (0x828)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 (0x82C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 (0x830)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 (0x834)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 (0x838)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 (0x83C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 (0x840)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 (0x844)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 (0x848)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 (0x84C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 (0x850)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 (0x854)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 (0x858)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 (0x85C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 (0x860)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 (0x864)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 (0x868)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 (0x86C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 (0x870)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 (0x874)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 (0x878)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 (0x87C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0  (0x880)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1  (0x884)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2  (0x888)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3  (0x88C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0  (0x890)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1  (0x894)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2  (0x898)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3  (0x89C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0  (0x8A0)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1  (0x8A4)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2  (0x8A8)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3  (0x8AC)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0  (0x8B0)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1  (0x8B4)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2  (0x8B8)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3  (0x8BC)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 (0x900)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 (0x904)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 (0x908)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 (0x90C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 (0x910)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 (0x914)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 (0x918)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 (0x91C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 (0x920)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 (0x924)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 (0x928)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 (0x92C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 (0x930)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 (0x934)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 (0x938)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 (0x93C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 (0x940)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 (0x944)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 (0x948)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 (0x94C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 (0x950)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 (0x954)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 (0x958)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 (0x95C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 (0x960)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 (0x964)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 (0x968)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 (0x96C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 (0x970)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 (0x974)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 (0x978)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 (0x97C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0  (0x980)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1  (0x984)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2  (0x988)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3  (0x98C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0  (0x990)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1  (0x994)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2  (0x998)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3  (0x99C)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0  (0x9A0)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1  (0x9A4)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2  (0x9A8)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3  (0x9AC)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0  (0x9B0)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1  (0x9B4)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2  (0x9B8)
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3  (0x9BC)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 (0xA00)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 (0xA04)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 (0xA08)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 (0xA10)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 (0xA14)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 (0xA18)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 (0xA20)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 (0xA24)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 (0xA28)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 (0xA30)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 (0xA34)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 (0xA38)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 (0xA40)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 (0xA44)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 (0xA48)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 (0xA50)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 (0xA54)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 (0xA58)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 (0xA60)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 (0xA64)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 (0xA68)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 (0xA70)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 (0xA74)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 (0xA78)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 (0xB00)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 (0xB04)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 (0xB08)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 (0xB10)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 (0xB14)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 (0xB18)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 (0xB20)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 (0xB24)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 (0xB28)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 (0xB30)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 (0xB34)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 (0xB38)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 (0xB40)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 (0xB44)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 (0xB48)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 (0xB50)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 (0xB54)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 (0xB58)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 (0xB60)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 (0xB64)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 (0xB68)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 (0xB70)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 (0xB74)
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 (0xB78)
+#define EMC_PMACRO_IB_VREF_DQ_0                   (0xBE0)
+#define EMC_PMACRO_IB_VREF_DQ_1                   (0xBE4)
+#define EMC_PMACRO_IB_VREF_DQS_0                  (0xBF0)
+#define EMC_PMACRO_IB_VREF_DQS_1                  (0xBF4)
+#define EMC_PMACRO_DDLL_LONG_CMD_0                (0xC00)
+#define EMC_PMACRO_DDLL_LONG_CMD_1                (0xC04)
+#define EMC_PMACRO_DDLL_LONG_CMD_2                (0xC08)
+#define EMC_PMACRO_DDLL_LONG_CMD_3                (0xC0C)
+#define EMC_PMACRO_DDLL_LONG_CMD_4                (0xC10)
+#define EMC_PMACRO_DDLL_SHORT_CMD_0               (0xC20)
+#define EMC_PMACRO_DDLL_SHORT_CMD_1               (0xC24)
+#define EMC_PMACRO_DDLL_SHORT_CMD_2               (0xC28)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0                (0xC30)
+#define EMC_PMACRO_VTTGEN_CTRL_0                  (0xC34)
+#define EMC_PMACRO_VTTGEN_CTRL_1                  (0xC38)
+#define EMC_PMACRO_BG_BIAS_CTRL_0                 (0xC3C)
+#define EMC_PMACRO_PAD_CFG_CTRL                   (0xC40)
+#define EMC_PMACRO_ZCTRL                          (0xC44)
+#define EMC_PMACRO_RX_TERM                        (0xC48)
+#define EMC_PMACRO_CMD_TX_DRV                     (0xC4C)
+#define EMC_PMACRO_CMD_PAD_RX_CTRL                (0xC50)
+#define EMC_PMACRO_DATA_PAD_RX_CTRL               (0xC54)
+#define EMC_PMACRO_CMD_RX_TERM_MODE               (0xC58)
+#define EMC_PMACRO_DATA_RX_TERM_MODE              (0xC5C)
+#define EMC_PMACRO_CMD_PAD_TX_CTRL                (0xC60)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL               (0xC64)
+#define EMC_PMACRO_COMMON_PAD_TX_CTRL             (0xC68)
+#define EMC_PMACRO_DSR_VTTGEN_CTRL_0              (0xC6C)
+#define EMC_PMACRO_DQ_TX_DRV                      (0xC70)
+#define EMC_PMACRO_CA_TX_DRV                      (0xC74)
+#define EMC_PMACRO_AUTOCAL_CFG_COMMON             (0xC78)
+#define EMC_PMACRO_BRICK_MAPPING_0                (0xC80)
+#define EMC_PMACRO_BRICK_MAPPING_1                (0xC84)
+#define EMC_PMACRO_BRICK_MAPPING_2                (0xC88)
+#define EMC_PMACRO_DDLL_PERIODIC_OFFSET           (0xCE8)
+#define EMC_PMACRO_VTTGEN_CTRL_2                  (0xCF0)
+#define EMC_PMACRO_IB_RXRT                        (0xCF4)
+#define EMC_PMACRO_TRAINING_CTRL_0                (0xCF8)
+#define EMC_PMACRO_TRAINING_CTRL_1                (0xCFC)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_0             (0xD40)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_1             (0xD44)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_2             (0xD48)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_3             (0xD4C)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_4             (0xD50)
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_5             (0xD54)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_0              (0xD60)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_1              (0xD64)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_2              (0xD68)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_3              (0xD6C)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_4              (0xD70)
+#define EMC_PMACRO_PERBIT_RFU_CTRL_5              (0xD74)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_0             (0xD80)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_1             (0xD84)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_2             (0xD88)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_3             (0xD8C)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_4             (0xD90)
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_5             (0xD94)
+#define EMC_TRAINING_CMD                          (0xE00)
+#define EMC_TRAINING_CTRL                         (0xE04)
+#define EMC_TRAINING_STATUS                       (0xE08)
+#define EMC_TRAINING_QUSE_CORS_CTRL               (0xE0C)
+#define EMC_TRAINING_QUSE_FINE_CTRL               (0xE10)
+#define EMC_TRAINING_QUSE_CTRL_MISC               (0xE14)
+#define EMC_TRAINING_WRITE_FINE_CTRL              (0xE18)
+#define EMC_TRAINING_WRITE_CTRL_MISC              (0xE1C)
+#define EMC_TRAINING_WRITE_VREF_CTRL              (0xE20)
+#define EMC_TRAINING_READ_FINE_CTRL               (0xE24)
+#define EMC_TRAINING_READ_CTRL_MISC               (0xE28)
+#define EMC_TRAINING_READ_VREF_CTRL               (0xE2C)
+#define EMC_TRAINING_CA_FINE_CTRL                 (0xE30)
+#define EMC_TRAINING_CA_CTRL_MISC                 (0xE34)
+#define EMC_TRAINING_CA_CTRL_MISC1                (0xE38)
+#define EMC_TRAINING_CA_VREF_CTRL                 (0xE3C)
+#define EMC_TRAINING_SETTLE                       (0xE44)
+#define EMC_TRAINING_MPC                          (0xE5C)
+#define EMC_TRAINING_PATRAM_CTRL                  (0xE60)
+#define EMC_TRAINING_PATRAM_DQ                    (0xE64)
+#define EMC_TRAINING_PATRAM_DMI                   (0xE68)
+#define EMC_TRAINING_VREF_SETTLE                  (0xE6C)
+#define EMC_TRAINING_OPT_CA_VREF                  (0xEC0)
+#define EMC_TRAINING_OPT_DQ_OB_VREF               (0xEC4)
+#define EMC_TRAINING_QUSE_VREF_CTRL               (0xED0)
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0        (0xED4)
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1        (0xED8)
+
 
 #define EMC_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (EMC, NAME)
 #define EMC_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (EMC, NAME, VALUE)
@@ -54,6 +552,8 @@
 #define DEFINE_EMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
 #define DEFINE_EMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
 
+DEFINE_EMC_REG_BIT_ENUM(DBG_WRITE_MUX, 1, ASSEMBLY, ACTIVE);
+
 DEFINE_EMC_REG_BIT_ENUM(CFG_DYN_SELF_REF, 28, DISABLED, ENABLED);
 DEFINE_EMC_REG_BIT_ENUM(CFG_DRAM_ACPD,    29, NO_POWERDOWN, ACTIVE_POWERDOWN);
 

libraries/libvapours/include/vapours/tegra/tegra_mc.hpp

@@ -32,6 +32,12 @@
 #define MC_SMMU_PTC_FLUSH_0                     (0x034)
 #define MC_EMEM_CFG                             (0x050)
 #define MC_EMEM_ADR_CFG                         (0x054)
+#define MC_EMEM_ADR_CFG_DEV0                    (0x058)
+#define MC_EMEM_ADR_CFG_DEV1                    (0x05C)
+#define MC_EMEM_ADR_CFG_CHANNEL_MASK            (0x060)
+#define MC_EMEM_ADR_CFG_BANK_MASK_0             (0x064)
+#define MC_EMEM_ADR_CFG_BANK_MASK_1             (0x068)
+#define MC_EMEM_ADR_CFG_BANK_MASK_2             (0x06C)
 #define MC_EMEM_ARB_CFG                         (0x090)
 #define MC_EMEM_ARB_OUTSTANDING_REQ             (0x094)
 #define MC_EMEM_ARB_TIMING_RCD                  (0x098)
@@ -52,6 +58,11 @@
 #define MC_EMEM_ARB_MISC0                       (0x0D8)
 #define MC_EMEM_ARB_MISC1                       (0x0DC)
 #define MC_EMEM_ARB_RING1_THROTTLE              (0x0E0)
+#define MC_EMEM_ARB_OVERRIDE                    (0x0E8)
+#define MC_EMEM_ARB_RSV                         (0x0EC)
+#define MC_CLKEN_OVERRIDE                       (0x0F4)
+#define MC_TIMING_CONTROL_DBG                   (0x0F8)
+#define MC_TIMING_CONTROL                       (0x0FC)
 #define MC_CLIENT_HOTRESET_CTRL                 (0x200)
 #define MC_CLIENT_HOTRESET_STATUS               (0x204)
 #define MC_SMMU_AFI_ASID                        (0x238)
@@ -95,6 +106,7 @@
 #define MC_LATENCY_ALLOWANCE_SDMMCAB_0          (0x3C4)
 #define MC_LATENCY_ALLOWANCE_NVDEC_0            (0x3D8)
 #define MC_LATENCY_ALLOWANCE_GPU2_0             (0x3E8)
+#define MC_VIDEO_PROTECT_VPR_OVERRIDE           (0x418)
 #define MC_DIS_PTSA_RATE                        (0x41C)
 #define MC_DIS_PTSA_MIN                         (0x420)
 #define MC_DIS_PTSA_MAX                         (0x424)
@@ -142,6 +154,7 @@
 #define MC_JPG_PTSA_RATE                        (0x584)
 #define MC_JPG_PTSA_MIN                         (0x588)
 #define MC_JPG_PTSA_MAX                         (0x58C)
+#define MC_VIDEO_PROTECT_VPR_OVERRIDE1          (0x590)
 #define MC_GK2_PTSA_RATE                        (0x610)
 #define MC_GK2_PTSA_MIN                         (0x614)
 #define MC_GK2_PTSA_MAX                         (0x618)
@@ -151,6 +164,8 @@
 #define MC_HDAPC_PTSA_RATE                      (0x628)
 #define MC_HDAPC_PTSA_MIN                       (0x62C)
 #define MC_HDAPC_PTSA_MAX                       (0x630)
+#define MC_VIDEO_PROTECT_BOM                    (0x648)
+#define MC_EMEM_CFG_ACCESS_CTRL                 (0x664)
 #define MC_SEC_CARVEOUT_BOM                     (0x670)
 #define MC_SEC_CARVEOUT_SIZE_MB                 (0x674)
 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A   (0x690)
@@ -165,9 +180,13 @@
 #define MC_EMEM_ARB_REFPB_BANK_CTRL             (0x6F4)
 #define MC_UNTRANSLATED_REGION_CHECK            (0x948)
 #define MC_PTSA_GRANT_DECREMENT                 (0x960)
+#define MC_EMEM_ARB_OVERRIDE_1                  (0x968)
 #define MC_CLIENT_HOTRESET_CTRL_1               (0x970)
 #define MC_CLIENT_HOTRESET_STATUS_1             (0x974)
+#define MC_VIDEO_PROTECT_BOM_ADR_HI             (0x978)
 #define MC_SMMU_PTC_FLUSH_1                     (0x9B8)
+#define MC_SEC_CARVEOUT_ADR_HI                  (0x9D4)
+#define MC_DA_CONFIG0                           (0x9DC)
 #define MC_SMMU_DC1_ASID                        (0xA88)
 #define MC_SMMU_SDMMC1A_ASID                    (0xA94)
 #define MC_SMMU_SDMMC2A_ASID                    (0xA98)
@@ -200,6 +219,7 @@
 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7        (0xBEC)
 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS      (0xC00)
 
+
 #define MC_SMMU_TLB_CONFIG                                  (0x014)
 #define MC_SMMU_PTC_CONFIG                                  (0x018)
 

libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp

@@ -46,6 +46,7 @@
 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK    (0x0DC)
 #define APBDEV_PMC_WAKE_DELAY            (0x0E0)
 #define APBDEV_PMC_PWR_DET_VAL           (0x0E4)
+#define APBDEV_PMC_DDR_PWR               (0x0E8)
 #define APBDEV_PMC_CRYPTO_OP             (0x0F4)
 #define APBDEV_PMC_SCRATCH31             (0x118)
 #define APBDEV_PMC_SCRATCH32             (0x11C)
@@ -64,12 +65,15 @@
 #define APBDEV_PMC_IO_DPD2_REQ           (0x1C0)
 #define APBDEV_PMC_IO_DPD2_STATUS        (0x1C4)
 #define APBDEV_PMC_SEL_DPD_TIM           (0x1C8)
+#define APBDEV_PMC_VDDP_SEL              (0x1CC)
+#define APBDEV_PMC_DDR_CFG               (0x1D0)
 #define APBDEV_PMC_SCRATCH45             (0x234)
 #define APBDEV_PMC_SCRATCH46             (0x238)
 #define APBDEV_PMC_SCRATCH49             (0x244)
 #define APBDEV_PMC_TSC_MULT              (0x2B4)
 #define APBDEV_PMC_STICKY_BITS           (0x2C0)
 #define APBDEV_PMC_WEAK_BIAS             (0x2C8)
+#define APBDEV_PMC_REG_SHORT             (0x2CC)
 #define APBDEV_PMC_GPU_RG_CNTRL          (0x2D4)
 #define APBDEV_PMC_CNTRL2                (0x440)
 #define APBDEV_PMC_FUSE_CTRL             (0x450)
@@ -125,6 +129,7 @@
 #define APBDEV_PMC_SECURE_SCRATCH115     (0xB24)
 #define APBDEV_PMC_SECURE_SCRATCH119     (0xB34)
 
+/* Mariko. */
 #define APBDEV_PMC_TZRAM_PWR_CNTRL       (0xBE8)
 #define APBDEV_PMC_TZRAM_SEC_DISABLE     (0xBEC)
 #define APBDEV_PMC_TZRAM_NON_SEC_DISABLE (0xBF0)