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kern: rename CacheHelper operation for accuracy
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parent
595c6dbe8f
commit
3ec9a9e59f
2 changed files with 8 additions and 8 deletions
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@ -88,7 +88,7 @@ namespace ams::kern::arch::arm64::cpu {
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public:
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public:
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enum class Operation {
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enum class Operation {
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Idle,
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Idle,
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InvalidateInstructionCache,
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InstructionMemoryBarrier,
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StoreDataCache,
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StoreDataCache,
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FlushDataCache,
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FlushDataCache,
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};
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};
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@ -160,7 +160,7 @@ namespace ams::kern::arch::arm64::cpu {
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constexpr u64 AllCoresMask = (1ul << cpu::NumCores) - 1ul;
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constexpr u64 AllCoresMask = (1ul << cpu::NumCores) - 1ul;
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const u64 other_cores_mask = AllCoresMask & ~(1ul << GetCurrentCoreId());
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const u64 other_cores_mask = AllCoresMask & ~(1ul << GetCurrentCoreId());
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if ((op == Operation::InvalidateInstructionCache) || (Kernel::GetState() == Kernel::State::Initializing)) {
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if ((op == Operation::InstructionMemoryBarrier) || (Kernel::GetState() == Kernel::State::Initializing)) {
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/* Check that there's no on-going operation. */
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/* Check that there's no on-going operation. */
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MESOSPHERE_ABORT_UNLESS(this->operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(this->operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(this->target_cores == 0);
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MESOSPHERE_ABORT_UNLESS(this->target_cores == 0);
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@ -286,7 +286,7 @@ namespace ams::kern::arch::arm64::cpu {
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switch (this->operation) {
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switch (this->operation) {
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case Operation::Idle:
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case Operation::Idle:
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break;
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break;
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case Operation::InvalidateInstructionCache:
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case Operation::InstructionMemoryBarrier:
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InstructionMemoryBarrier();
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InstructionMemoryBarrier();
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break;
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break;
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case Operation::StoreDataCache:
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case Operation::StoreDataCache:
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@ -423,8 +423,8 @@ namespace ams::kern::arch::arm64::cpu {
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R_TRY(InvalidateInstructionCacheRange(start, end));
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R_TRY(InvalidateInstructionCacheRange(start, end));
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/* Request the interrupt helper to invalidate, too. */
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/* Request the interrupt helper to perform an instruction memory barrier. */
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g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InvalidateInstructionCache);
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g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InstructionMemoryBarrier);
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return ResultSuccess();
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return ResultSuccess();
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}
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}
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@ -436,8 +436,8 @@ namespace ams::kern::arch::arm64::cpu {
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InvalidateEntireInstructionCacheGlobalImpl();
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InvalidateEntireInstructionCacheGlobalImpl();
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EnsureInstructionConsistency();
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EnsureInstructionConsistency();
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/* Request the interrupt helper to invalidate, too. */
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/* Request the interrupt helper to perform an instruction memory barrier. */
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g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InvalidateInstructionCache);
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g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InstructionMemoryBarrier);
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}
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}
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void InitializeInterruptThreads(s32 core_id) {
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void InitializeInterruptThreads(s32 core_id) {
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@ -2167,7 +2167,7 @@ namespace ams::kern {
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/* Copy remaining data. */
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/* Copy remaining data. */
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if (cur_size > 0) {
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if (cur_size > 0) {
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R_UNLESS(UserspaceAccess::CopyMemoryFromUser(GetVoidPointer(GetLinearMappedVirtualAddress(cur_addr)), buffer, cur_size), svc::ResultInvalidCurrentMemory());
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R_UNLESS(UserspaceAccess::CopyMemoryFromUser(GetVoidPointer(GetLinearMappedVirtualAddress(cur_addr)), buffer, cur_size), svc::ResultInvalidCurrentMemory());
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cpu::StoreDataCache(GetVoidPointer(GetLinearMappedVirtualAddress(cur_addr)), copy_size);
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cpu::StoreDataCache(GetVoidPointer(GetLinearMappedVirtualAddress(cur_addr)), cur_size);
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}
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}
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return ResultSuccess();
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return ResultSuccess();
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