mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-22 20:06:40 +00:00
kern: add hardware single step extension
This commit is contained in:
parent
904ab19823
commit
4075d24e0c
10 changed files with 226 additions and 4 deletions
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@ -14,6 +14,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <mesosphere/kern_build_config.hpp>
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/* TODO: Different header for this? */
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#define AMS_KERN_NUM_SUPERVISOR_CALLS 0xC0
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@ -30,6 +31,10 @@
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#define THREAD_STACK_PARAMETERS_IS_IN_EXCEPTION_HANDLER 0x2D
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#define THREAD_STACK_PARAMETERS_IS_PINNED 0x2E
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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#define THREAD_STACK_PARAMETERS_IS_SINGLE_STEP 0x2F
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#endif
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/* ams::kern::arch::arm64::KThreadContext, https://github.com/Atmosphere-NX/Atmosphere/blob/master/libraries/libmesosphere/include/mesosphere/arch/arm64/kern_k_thread_context.hpp */
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#define THREAD_CONTEXT_SIZE 0x290
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#define THREAD_CONTEXT_CPU_REGISTERS 0x000
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@ -31,3 +31,4 @@
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//#define MESOSPHERE_BUILD_FOR_TRACING
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#define MESOSPHERE_ENABLE_PANIC_REGISTER_DUMP
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#define MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP
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@ -92,6 +92,9 @@ namespace ams::kern {
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bool is_calling_svc;
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bool is_in_exception_handler;
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bool is_pinned;
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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bool is_single_step;
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#endif
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};
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static_assert(alignof(StackParameters) == 0x10);
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static_assert(sizeof(StackParameters) == THREAD_STACK_PARAMETERS_SIZE);
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@ -106,6 +109,10 @@ namespace ams::kern {
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static_assert(__builtin_offsetof(StackParameters, is_in_exception_handler) == THREAD_STACK_PARAMETERS_IS_IN_EXCEPTION_HANDLER);
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static_assert(__builtin_offsetof(StackParameters, is_pinned) == THREAD_STACK_PARAMETERS_IS_PINNED);
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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static_assert(__builtin_offsetof(StackParameters, is_single_step) == THREAD_STACK_PARAMETERS_IS_SINGLE_STEP);
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#endif
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struct QueueEntry {
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private:
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KThread *m_prev;
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@ -325,6 +332,25 @@ namespace ams::kern {
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return this->GetStackParameters().current_svc_id;
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}
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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ALWAYS_INLINE void SetSingleStep() {
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MESOSPHERE_ASSERT_THIS();
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this->GetStackParameters().is_single_step = true;
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}
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ALWAYS_INLINE void ClearSingleStep() {
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MESOSPHERE_ASSERT_THIS();
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this->GetStackParameters().is_single_step = false;
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}
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ALWAYS_INLINE bool IsSingleStep() const {
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MESOSPHERE_ASSERT_THIS();
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return this->GetStackParameters().is_single_step;
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}
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#endif
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ALWAYS_INLINE void RegisterDpc(DpcFlag flag) {
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this->GetStackParameters().dpc_flags.fetch_or(flag);
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}
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@ -15,6 +15,39 @@
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*/
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#include <mesosphere/kern_select_assembly_offsets.h>
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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.macro disable_single_step, scratch
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/* Clear MDSCR_EL1.SS. */
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mrs \scratch, mdscr_el1
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bic \scratch, \scratch, #1
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msr mdscr_el1, \scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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/* Check if single-step is requested. */
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ldrb \scratch1, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_IS_SINGLE_STEP)]
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tbz \scratch1, #0, .skip_single_step\@
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/* If single-step is requested, enable the single-step machine by setting MDSCR_EL1.SS. */
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mrs \scratch2, mdscr_el1
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orr \scratch2, \scratch2, #1
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msr mdscr_el1, \scratch2
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/* Since we're returning from an exception, set SPSR.SS so we actually advance an instruction. */
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orr \spsr_value, \spsr_value, #(1 << 21)
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isb
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.skip_single_step\@:
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.endm
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#else
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.macro disable_single_step, scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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.endm
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#endif
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/* ams::kern::svc::CallReturnFromException64(Result result) */
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.section .text._ZN3ams4kern3svc25CallReturnFromException64Ev, "ax", %progbits
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.global _ZN3ams4kern3svc25CallReturnFromException64Ev
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@ -89,6 +122,9 @@ _ZN3ams4kern3svc14RestoreContextEm:
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ldp x30, x8, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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ldp x9, x10, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x11, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x10
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msr sp_el0, x8
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msr elr_el1, x9
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msr spsr_el1, x10
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@ -16,6 +16,39 @@
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#include <mesosphere/kern_build_config.hpp>
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#include <mesosphere/kern_select_assembly_offsets.h>
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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.macro disable_single_step, scratch
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/* Clear MDSCR_EL1.SS. */
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mrs \scratch, mdscr_el1
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bic \scratch, \scratch, #1
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msr mdscr_el1, \scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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/* Check if single-step is requested. */
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ldrb \scratch1, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_IS_SINGLE_STEP)]
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tbz \scratch1, #0, .skip_single_step\@
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/* If single-step is requested, enable the single-step machine by setting MDSCR_EL1.SS. */
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mrs \scratch2, mdscr_el1
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orr \scratch2, \scratch2, #1
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msr mdscr_el1, \scratch2
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/* Since we're returning from an SVC, make sure SPSR.SS is cleared so we break instantly on the instruction after the SVC. */
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bic \spsr_value, \spsr_value, #(1 << 21)
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isb
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.skip_single_step\@:
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.endm
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#else
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.macro disable_single_step, scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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.endm
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#endif
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/* ams::kern::arch::arm64::SvcHandler64() */
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.section .text._ZN3ams4kern4arch5arm6412SvcHandler64Ev, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6412SvcHandler64Ev
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stp x8, x9, [sp, #(EXCEPTION_CONTEXT_SP_PC)]
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stp x10, x11, [sp, #(EXCEPTION_CONTEXT_PSR_TPIDR)]
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/* Disable single-step. */
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disable_single_step x8
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/* Check if the SVC index is out of range. */
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mrs x8, esr_el1
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and x8, x8, #0xFF
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ldp x30, x8, [sp, #(EXCEPTION_CONTEXT_X30_SP)]
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ldp x9, x10, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x11, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x10
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msr sp_el0, x8
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msr elr_el1, x9
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msr spsr_el1, x10
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ldp x9, x10, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x11, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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ldr x18, [sp, #(EXCEPTION_CONTEXT_X18)]
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check_enable_single_step w12, x12, x10
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msr sp_el0, x8
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msr elr_el1, x9
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msr spsr_el1, x10
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@ -260,6 +302,9 @@ _ZN3ams4kern4arch5arm6412SvcHandler32Ev:
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stp x12, x13, [sp, #(EXCEPTION_CONTEXT_X12_X13)]
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stp x14, xzr, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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/* Disable single-step. */
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disable_single_step x8
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/* Check if the SVC index is out of range. */
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mrs x16, esr_el1
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and x16, x16, #0xFF
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/* Restore registers. */
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ldp x17, x20, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x19, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x20
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msr elr_el1, x17
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msr spsr_el1, x20
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msr tpidr_el0, x19
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ldp x14, xzr, [sp, #(EXCEPTION_CONTEXT_X14_X15)]
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ldp x17, x20, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x19, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w21, x21, x20
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msr elr_el1, x17
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msr spsr_el1, x20
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msr tpidr_el0, x19
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@ -372,6 +372,14 @@ namespace ams::kern {
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new_state = state;
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}
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/* Clear single step on all threads. */
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{
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auto end = target->GetThreadList().end();
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for (auto it = target->GetThreadList().begin(); it != end; ++it) {
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it->ClearSingleStep();
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}
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}
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/* Detach from the process. */
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target->ClearDebugObject(new_state);
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m_process = nullptr;
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}
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}
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/* Update thread single-step state. */
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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{
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if ((context_flags & ams::svc::ThreadContextFlag_SetSingleStep) != 0) {
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/* Set single step. */
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thread->SetSingleStep();
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/* If no other thread flags are present, we're done. */
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R_SUCCEED_IF((context_flags & ~ams::svc::ThreadContextFlag_SetSingleStep) == 0);
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} else if ((context_flags & ams::svc::ThreadContextFlag_ClearSingleStep) != 0) {
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/* Clear single step. */
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thread->ClearSingleStep();
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/* If no other thread flags are present, we're done. */
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R_SUCCEED_IF((context_flags & ~ams::svc::ThreadContextFlag_ClearSingleStep) == 0);
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}
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}
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#endif
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/* Verify that the thread's svc state is valid. */
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if (thread->IsCallingSvc()) {
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const u8 svc_id = thread->GetSvcId();
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{
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auto end = process->GetThreadList().end();
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for (auto it = process->GetThreadList().begin(); it != end; ++it) {
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/* Clear the thread's single-step state. */
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it->ClearSingleStep();
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if (resume) {
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/* If the process isn't crashed, resume threads. */
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it->Resume(KThread::SuspendType_Debug);
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/* Set the process as breaked. */
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process->SetDebugBreak();
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/* If the event is an exception, set the result. */
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/* If the event is an exception, set the result and clear single step. */
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if (event == ams::svc::DebugEvent_Exception) {
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GetCurrentThread().SetDebugExceptionResult(ResultSuccess());
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GetCurrentThread().ClearSingleStep();
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}
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/* Exit our retry loop. */
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@ -186,7 +186,24 @@ namespace ams::kern::svc {
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R_UNLESS(KTargetSystem::IsDebugMode(), svc::ResultNotImplemented());
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/* Validate the context flags. */
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R_UNLESS((context_flags | ams::svc::ThreadContextFlag_All) == ams::svc::ThreadContextFlag_All, svc::ResultInvalidEnumValue());
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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{
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/* Check that the flags are a subset of the allowable. */
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constexpr u32 AllFlagsMask = ams::svc::ThreadContextFlag_All | ams::svc::ThreadContextFlag_SetSingleStep | ams::svc::ThreadContextFlag_ClearSingleStep;
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R_UNLESS((context_flags | AllFlagsMask) == AllFlagsMask, svc::ResultInvalidEnumValue());
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/* Check that thread isn't both setting and clearing single step. */
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const bool set_ss = (context_flags & ams::svc::ThreadContextFlag_SetSingleStep) != 0;
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const bool clear_ss = (context_flags & ams::svc::ThreadContextFlag_ClearSingleStep) != 0;
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R_UNLESS(!(set_ss && clear_ss), svc::ResultInvalidEnumValue());
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}
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#else
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{
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/* Check that the flags are a subset of the allowable. */
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R_UNLESS((context_flags | ams::svc::ThreadContextFlag_All) == ams::svc::ThreadContextFlag_All, svc::ResultInvalidEnumValue());
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}
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#endif
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/* Copy the thread context from userspace. */
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ams::svc::ThreadContext context;
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@ -271,6 +271,16 @@ namespace ams::kern::svc {
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*out = KTraceValue;
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}
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break;
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case ams::svc::MesosphereMetaInfo_IsSingleStepEnabled:
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{
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/* Return whether the kernel supports hardware single step. */
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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*out = 1;
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#else
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*out = 0;
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#endif
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}
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break;
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default:
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return svc::ResultInvalidCombination();
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}
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@ -174,8 +174,9 @@ namespace ams::svc {
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};
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enum MesosphereMetaInfo : u64 {
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MesosphereMetaInfo_KernelVersion = 0,
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MesosphereMetaInfo_IsKTraceEnabled = 1,
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MesosphereMetaInfo_KernelVersion = 0,
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MesosphereMetaInfo_IsKTraceEnabled = 1,
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MesosphereMetaInfo_IsSingleStepEnabled = 2,
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};
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enum SystemInfoType : u32 {
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ThreadContextFlag_FpuControl = (1 << 3),
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ThreadContextFlag_All = (ThreadContextFlag_General | ThreadContextFlag_Control | ThreadContextFlag_Fpu | ThreadContextFlag_FpuControl),
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ThreadContextFlag_SetSingleStep = (1u << 30),
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ThreadContextFlag_ClearSingleStep = (1u << 31),
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};
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enum ContinueFlag : u32 {
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@ -15,6 +15,39 @@
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*/
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#include <mesosphere/kern_select_assembly_offsets.h>
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#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
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.macro disable_single_step, scratch
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/* Clear MDSCR_EL1.SS. */
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mrs \scratch, mdscr_el1
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bic \scratch, \scratch, #1
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msr mdscr_el1, \scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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/* Check if single-step is requested. */
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ldrb \scratch1, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_IS_SINGLE_STEP)]
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tbz \scratch1, #0, .skip_single_step\@
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/* If single-step is requested, enable the single-step machine by setting MDSCR_EL1.SS. */
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mrs \scratch2, mdscr_el1
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orr \scratch2, \scratch2, #1
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msr mdscr_el1, \scratch2
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/* Since we're returning from an exception, set SPSR.SS so we actually advance an instruction. */
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orr \spsr_value, \spsr_value, #(1 << 21)
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isb
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.skip_single_step\@:
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.endm
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#else
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.macro disable_single_step, scratch
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.endm
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.macro check_enable_single_step, scratch1, scratch2, spsr_value
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.endm
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#endif
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/* ams::kern::arch::arm64::EL1IrqExceptionHandler() */
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.section .text._ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv, "ax", %progbits
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.global _ZN3ams4kern4arch5arm6422EL1IrqExceptionHandlerEv
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@ -100,6 +133,8 @@ _ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv:
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stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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disable_single_step x0
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/* Invoke KInterruptManager::HandleInterrupt(bool user_mode). */
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ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
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mov x0, #1
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@ -110,6 +145,8 @@ _ZN3ams4kern4arch5arm6422EL0IrqExceptionHandlerEv:
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ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
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ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
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check_enable_single_step w0, x0, x22
|
||||
|
||||
msr sp_el0, x20
|
||||
msr elr_el1, x21
|
||||
msr spsr_el1, x22
|
||||
|
@ -202,6 +239,8 @@ _ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv:
|
|||
stp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
||||
str x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
||||
|
||||
disable_single_step x16
|
||||
|
||||
/* Call ams::kern::arch::arm64::HandleException(ams::kern::arch::arm64::KExceptionContext *) */
|
||||
ldr x18, [sp, #(EXCEPTION_CONTEXT_SIZE + THREAD_STACK_PARAMETERS_CUR_THREAD)]
|
||||
mov x0, sp
|
||||
|
@ -212,6 +251,8 @@ _ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv:
|
|||
ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
|
||||
ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
|
||||
|
||||
check_enable_single_step w0, x0, x22
|
||||
|
||||
msr sp_el0, x20
|
||||
msr elr_el1, x21
|
||||
msr spsr_el1, x22
|
||||
|
|
Loading…
Reference in a new issue