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Code Issues Releases Activity

kern: update set/way cache operations for new semantics

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This commit is contained in:
Michael Scire 2021-04-07 10:05:09 -07:00 committed by SciresM
parent 6e4664ee05
commit 44ccbc2a7b
1 changed files with 26 additions and 5 deletions
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31
libraries/libmesosphere/source/arch/arm64/kern_cpu.cpp
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@ -283,6 +283,16 @@ namespace ams::kern::arch::arm64::cpu {
} }
} }
void StoreDataCacheBySetWay(int level) {
PerformCacheOperationBySetWayImpl<false>(level, StoreDataCacheLineBySetWayImpl);
cpu::DataSynchronizationBarrier();
}
void FlushDataCacheBySetWay(int level) {
PerformCacheOperationBySetWayImpl<false>(level, FlushDataCacheLineBySetWayImpl);
cpu::DataSynchronizationBarrier();
}
void KCacheHelperInterruptHandler::ProcessOperation() { void KCacheHelperInterruptHandler::ProcessOperation() {
switch (m_operation) { switch (m_operation) {
case Operation::Idle: case Operation::Idle:
@ -291,12 +301,10 @@ namespace ams::kern::arch::arm64::cpu {
InstructionMemoryBarrier(); InstructionMemoryBarrier();
break; break;
case Operation::StoreDataCache: case Operation::StoreDataCache:
PerformCacheOperationBySetWayLocal<false>(StoreDataCacheLineBySetWayImpl); StoreDataCacheBySetWay(0);
DataSynchronizationBarrier();
break; break;
case Operation::FlushDataCache: case Operation::FlushDataCache:
PerformCacheOperationBySetWayLocal<false>(FlushDataCacheLineBySetWayImpl); FlushDataCacheBySetWay(0);
DataSynchronizationBarrier();
break; break;
} }
@ -374,7 +382,20 @@ namespace ams::kern::arch::arm64::cpu {
} }
void FlushEntireDataCache() { void FlushEntireDataCache() {
return PerformCacheOperationBySetWayShared<false>(FlushDataCacheLineBySetWayImpl); KScopedCoreMigrationDisable dm;
CacheLineIdRegisterAccessor clidr_el1;
const int levels_of_coherency = clidr_el1.GetLevelsOfCoherency();
/* Store cache from L2 up to the level of coherence (if there's an L3 cache or greater). */
for (int level = 2; level < levels_of_coherency; ++level) {
StoreDataCacheBySetWay(level - 1);
}
/* Flush cache from the level of coherence down to L2. */
for (int level = levels_of_coherency; level > 1; --level) {
FlushDataCacheBySetWay(level - 1);
}
} }
Result InvalidateDataCache(void *addr, size_t size) { Result InvalidateDataCache(void *addr, size_t size) {