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thermosphere: mmu: fix shareability

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TuxSH 2020-03-01 22:49:34 +00:00
parent 987731ea43
commit 47f343cda6
2 changed files with 6 additions and 71 deletions
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9
thermosphere/src/cpu/hvisor_cpu_mmu.hpp
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@ -38,8 +38,9 @@ namespace ams::hvisor::cpu {
}; };
// Multi-byte attributes... // Multi-byte attributes...
constexpr u64 MMU_ATTRINDEX(u64 idx) { return (idx & 8) << 2; } constexpr u64 MMU_ATTRINDX(u64 idx) { return (idx & 8) << 2; }
constexpr u64 MMU_MEMATTR(u64 attr) { return (attr & 0xF) << 2; } constexpr u64 MMU_MEMATTR(u64 attr) { return (attr & 0xF) << 2; }
constexpr u64 MMU_SH(u64 sh) { return (sh & 3) << 8; }
// Attributes. They are defined in a way that allows recursive page tables (assuming PBHA isn't used) // Attributes. They are defined in a way that allows recursive page tables (assuming PBHA isn't used)
enum MmuPteAttributes : u64 { enum MmuPteAttributes : u64 {
@ -66,9 +67,9 @@ namespace ams::hvisor::cpu {
MMU_AF = BITL(10), MMU_AF = BITL(10),
// SH[1:0] // SH[1:0]
MMU_NON_SHAREABLE = 0 << 8, MMU_NON_SHAREABLE = MMU_SH(0),
MMU_OUTER_SHAREABLE = 2 << 8, MMU_OUTER_SHAREABLE = MMU_SH(2),
MMU_INNER_SHAREABLE = 2 << 8, MMU_INNER_SHAREABLE = MMU_SH(3),
// AP[2:1], stage 1 only. AP[0] does not exist. // AP[2:1], stage 1 only. AP[0] does not exist.
MMU_AP_PRIV_RW = 0 << 6, MMU_AP_PRIV_RW = 0 << 6,

66
thermosphere/src/memory_map.h
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@ -1,66 +0,0 @@
/*
* Copyright (c) 2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "utils.h"
#define MEMORY_MAP_MEMTYPE_DEVICE_NGNRNE 0ul
#define MEMORY_MAP_MEMTYPE_NORMAL 1ul
#define MEMORY_MAP_MEMTYPE_DEVICE_NGNRE 2ul
#define MEMORY_MAP_MEMTYPE_NORMAL_UNCACHEABLE 3ul
#define MEMORY_MAP_MEMTYPE_NORMAL_GUEST_SLOT 4ul
#define MEMORY_MAP_VA_SPACE_SIZE 39ul
// The following few definitions depend on the value of MEMORY_MAP_VA_SPACE_SIZE:
#define MEMORY_MAP_SELF_L2_VA_RANGE 0x7FC0000000ul // = 511 << 31
#define MEMORY_MAP_SELF_L3_VA_RANGE 0x7FFFE00000ul // = 511 << 31 | 511 << 21
#define MEMORY_MAP_VA_TTBL 0x7FFFFFF000ul // = 511 << 31 | 511 << 21 | 511 << 12
#define MEMORY_MAP_VA_MAX 0x7FFFFFFFFFul // = all 39 bits set
#define MEMORY_MAP_VA_CRASH_STACKS_SIZE 0x1000ul
#define MEMORY_MAP_VA_IMAGE (MEMORY_MAP_SELF_L3_VA_RANGE + 0x10000)
#define MEMORY_MAP_VA_CRASH_STACKS_BOTTOM (MEMORY_MAP_SELF_L3_VA_RANGE + 0x40000)
#define MEMORY_MAP_VA_CRASH_STACKS_TOP (MEMORY_MAP_SELF_L3_VA_RANGE + 0x41000)
#define MEMORY_MAP_VA_GUEST_MEM (MEMORY_MAP_SELF_L3_VA_RANGE + 0x50000)
#define MEMORY_MAP_VA_STACKS_TOP (MEMORY_MAP_SELF_L3_VA_RANGE + 0x80000)
#define MEMORY_MAP_VA_MMIO_BASE MEMORY_MAP_VA_STACKS_TOP
#define MEMORY_MAP_VA_GICD MEMORY_MAP_VA_MMIO_BASE
#define MEMORY_MAP_VA_GICC (MEMORY_MAP_VA_MMIO_BASE + 0x1000)
#define MEMORY_MAP_VA_GICH (MEMORY_MAP_VA_MMIO_BASE + 0x3000)
#define MEMORY_MAP_VA_MMIO_PLAT_BASE (MEMORY_MAP_VA_MMIO_BASE + 0x90000)
typedef struct LoadImageLayout {
uintptr_t startPa;
size_t imageSize; // "image" includes "real" BSS but not tempbss
uintptr_t tempPa;
size_t maxTempSize;
size_t tempSize;
uintptr_t vbar;
} LoadImageLayout;
extern LoadImageLayout g_loadImageLayout;
uintptr_t memoryMapGetStackTop(u32 coreId);
// Non-reentrant
uintptr_t memoryMapPlatformMmio(uintptr_t pa, size_t size);