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https://github.com/Atmosphere-NX/Atmosphere.git
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boot: implement I2cBusAccessor
This commit is contained in:
Michael Scire
parent
967613a261
commit
4c5c78858c
7 changed files with 839 additions and 2 deletions
90
stratosphere/boot/source/i2c_driver/boot_pcv.cpp
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90
stratosphere/boot/source/i2c_driver/boot_pcv.cpp
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@ -0,0 +1,90 @@
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/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <switch.h>
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#include <stratosphere.hpp>
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#include "i2c_types.hpp"
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#include "i2c_registers.hpp"
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#include "boot_pcv.hpp"
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static I2cBus GetI2cBus(PcvModule module) {
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switch (module) {
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case PcvModule_I2C1:
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return I2cBus_I2c1;
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case PcvModule_I2C2:
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return I2cBus_I2c2;
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case PcvModule_I2C3:
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return I2cBus_I2c3;
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case PcvModule_I2C4:
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return I2cBus_I2c4;
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case PcvModule_I2C5:
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return I2cBus_I2c5;
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case PcvModule_I2C6:
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return I2cBus_I2c6;
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default:
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std::abort();
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}
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}
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void Pcv::Initialize() {
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/* Don't do anything. */
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}
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void Pcv::Finalize() {
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/* Don't do anything. */
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}
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Result Pcv::SetClockRate(PcvModule module, u32 hz) {
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/* Get clock/reset registers. */
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ClkRstRegisters regs;
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regs.SetBus(GetI2cBus(module));
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/* Set clock enabled/source. */
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SetRegisterBits(regs.clk_en_reg, regs.mask);
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ReadWriteRegisterBits(regs.clk_src_reg, 0x4, 0xFF);
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svcSleepThread(1000ul);
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ReadWriteRegisterBits(regs.clk_src_reg, 0, 0xE0000000);
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svcSleepThread(2000ul);
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return ResultSuccess;
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}
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Result Pcv::SetClockEnabled(PcvModule module, bool enabled) {
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return ResultSuccess;
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}
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Result Pcv::SetVoltageEnabled(u32 domain, bool enabled) {
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return ResultSuccess;
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}
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Result Pcv::SetVoltageValue(u32 domain, u32 voltage) {
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return ResultSuccess;
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}
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Result Pcv::SetReset(PcvModule module, bool reset) {
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/* Get clock/reset registers. */
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ClkRstRegisters regs;
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regs.SetBus(GetI2cBus(module));
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/* Set/clear reset. */
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if (reset) {
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SetRegisterBits(regs.rst_reg, regs.mask);
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} else {
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ClearRegisterBits(regs.rst_reg, regs.mask);
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}
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return ResultSuccess;
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}
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33
stratosphere/boot/source/i2c_driver/boot_pcv.hpp
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33
stratosphere/boot/source/i2c_driver/boot_pcv.hpp
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@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <switch.h>
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#include <stratosphere.hpp>
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/* pcv isn't alive at the time boot runs, but nn::i2c::driver needs nn::pcv. */
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/* These are the overrides N puts in boot. */
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class Pcv {
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public:
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static void Initialize();
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static void Finalize();
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static Result SetClockRate(PcvModule module, u32 hz);
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static Result SetClockEnabled(PcvModule module, bool enabled);
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static Result SetVoltageEnabled(u32 domain, bool enabled);
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static Result SetVoltageValue(u32 domain, u32 voltage);
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static Result SetReset(PcvModule module, bool reset);
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};
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494
stratosphere/boot/source/i2c_driver/i2c_bus_accessor.cpp
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494
stratosphere/boot/source/i2c_driver/i2c_bus_accessor.cpp
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@ -0,0 +1,494 @@
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/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <switch.h>
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#include <stratosphere.hpp>
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#include "i2c_bus_accessor.hpp"
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#include "boot_pcv.hpp"
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void I2cBusAccessor::Open(I2cBus bus, SpeedMode speed_mode) {
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std::scoped_lock<HosMutex> lk(this->open_mutex);
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/* Open new session. */
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this->open_sessions++;
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/* Ensure we're good if this isn't our first session. */
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if (this->open_sessions > 1) {
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if (this->speed_mode != speed_mode) {
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std::abort();
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}
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return;
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}
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/* Set all members for chosen bus. */
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{
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std::scoped_lock<HosMutex> lk(this->register_mutex);
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/* Set bus/registers. */
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this->SetBus(bus);
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/* Set pcv module. */
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switch (bus) {
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case I2cBus_I2c1:
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this->pcv_module = PcvModule_I2C1;
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break;
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case I2cBus_I2c2:
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this->pcv_module = PcvModule_I2C2;
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break;
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case I2cBus_I2c3:
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this->pcv_module = PcvModule_I2C3;
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break;
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case I2cBus_I2c4:
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this->pcv_module = PcvModule_I2C4;
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break;
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case I2cBus_I2c5:
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this->pcv_module = PcvModule_I2C5;
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break;
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case I2cBus_I2c6:
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this->pcv_module = PcvModule_I2C6;
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break;
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default:
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std::abort();
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}
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/* Set speed mode. */
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this->speed_mode = speed_mode;
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/* Setup interrupt event. */
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this->CreateInterruptEvent(bus);
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}
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}
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void I2cBusAccessor::Close() {
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std::scoped_lock<HosMutex> lk(this->open_mutex);
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/* Close current session. */
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this->open_sessions--;
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if (this->open_sessions > 0) {
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return;
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}
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/* Close interrupt event. */
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eventClose(&this->interrupt_event);
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/* Close PCV. */
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Pcv::Finalize();
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this->suspended = false;
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}
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void I2cBusAccessor::Suspend() {
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std::scoped_lock<HosMutex> lk(this->open_mutex);
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std::scoped_lock<HosMutex> lk_reg(this->register_mutex);
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if (!this->suspended) {
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this->suspended = true;
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if (this->pcv_module != PcvModule_I2C5) {
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this->DisableClock();
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}
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}
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}
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void I2cBusAccessor::Resume() {
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if (this->suspended) {
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this->DoInitialConfig();
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this->suspended = false;
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}
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}
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void I2cBusAccessor::DoInitialConfig() {
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std::scoped_lock<HosMutex> lk(this->register_mutex);
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if (this->pcv_module != PcvModule_I2C5) {
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Pcv::Initialize();
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}
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this->ResetController();
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this->SetClock(this->speed_mode);
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this->SetPacketMode();
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this->FlushFifos();
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}
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size_t I2cBusAccessor::GetOpenSessions() const {
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return this->open_sessions;
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}
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bool I2cBusAccessor::GetBusy() const {
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/* Nintendo has a loop here that calls a member function to check if busy, retrying a few times. */
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/* This member function does "return false". */
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/* We will not bother with the loop. */
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return false;
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}
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Result I2cBusAccessor::Send(const u8 *data, size_t num_bytes, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address) {
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std::scoped_lock<HosMutex> lk(this->register_mutex);
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const u8 *cur_src = data;
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size_t remaining = num_bytes;
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Result rc;
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/* Set interrupt enable, clear interrupt status. */
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WriteRegister(&this->i2c_registers->I2C_INTERRUPT_MASK_REGISTER_0, 0x8E);
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WriteRegister(&this->i2c_registers->I2C_INTERRUPT_STATUS_REGISTER_0, 0xFC);
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ON_SCOPE_EXIT { this->ClearInterruptMask(); };
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/* Send header. */
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this->WriteTransferHeader(TransferMode_Send, option, addressing_mode, slave_address, num_bytes);
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/* Send bytes. */
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while (true) {
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const u32 fifo_status = ReadRegister(&this->i2c_registers->I2C_FIFO_STATUS_0);
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const size_t fifo_cnt = (fifo_status >> 4);
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for (size_t fifo_idx = 0; remaining > 0 && fifo_idx < fifo_cnt; fifo_idx++) {
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const size_t cur_bytes = std::min(remaining, sizeof(u32));
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u32 val = 0;
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for (size_t i = 0; i < cur_bytes; i++) {
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val |= cur_src[i] << (8 * i);
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}
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WriteRegister(&this->i2c_registers->I2C_I2C_TX_PACKET_FIFO_0, val);
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cur_src += cur_bytes;
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remaining -= cur_bytes;
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}
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if (remaining == 0) {
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break;
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}
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eventClear(&this->interrupt_event);
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if (R_FAILED(eventWait(&this->interrupt_event, InterruptTimeout))) {
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this->HandleTransactionResult(ResultI2cBusBusy);
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eventClear(&this->interrupt_event);
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return ResultI2cTimedOut;
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}
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if (R_FAILED((rc = this->GetAndHandleTransactionResult()))) {
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return rc;
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}
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}
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WriteRegister(&this->i2c_registers->I2C_INTERRUPT_MASK_REGISTER_0, 0x8C);
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/* Wait for successful completion. */
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while (true) {
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if (R_FAILED((rc = this->GetAndHandleTransactionResult()))) {
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return rc;
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}
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/* Check PACKET_XFER_COMPLETE */
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const u32 interrupt_status = ReadRegister(&this->i2c_registers->I2C_INTERRUPT_STATUS_REGISTER_0);
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if (interrupt_status & 0x80) {
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if (R_FAILED((rc = this->GetAndHandleTransactionResult()))) {
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return rc;
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}
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break;
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}
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eventClear(&this->interrupt_event);
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if (R_FAILED(eventWait(&this->interrupt_event, InterruptTimeout))) {
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this->HandleTransactionResult(ResultI2cBusBusy);
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eventClear(&this->interrupt_event);
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return ResultI2cTimedOut;
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}
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}
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return ResultSuccess;
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}
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Result I2cBusAccessor::Receive(u8 *out_data, size_t num_bytes, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address) {
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std::scoped_lock<HosMutex> lk(this->register_mutex);
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u8 *cur_dst = out_data;
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size_t remaining = num_bytes;
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Result rc;
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/* Set interrupt enable, clear interrupt status. */
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WriteRegister(&this->i2c_registers->I2C_INTERRUPT_MASK_REGISTER_0, 0x8D);
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WriteRegister(&this->i2c_registers->I2C_INTERRUPT_STATUS_REGISTER_0, 0xFC);
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/* Send header. */
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this->WriteTransferHeader(TransferMode_Receive, option, addressing_mode, slave_address, num_bytes);
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/* Receive bytes. */
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while (remaining > 0) {
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eventClear(&this->interrupt_event);
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if (R_FAILED(eventWait(&this->interrupt_event, InterruptTimeout))) {
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this->HandleTransactionResult(ResultI2cBusBusy);
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this->ClearInterruptMask();
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eventClear(&this->interrupt_event);
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return ResultI2cTimedOut;
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}
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if (R_FAILED((rc = this->GetAndHandleTransactionResult()))) {
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return rc;
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}
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const u32 fifo_status = ReadRegister(&this->i2c_registers->I2C_FIFO_STATUS_0);
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const size_t fifo_cnt = std::min((remaining + 3) >> 2, static_cast<size_t>(fifo_status & 0xF));
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for (size_t fifo_idx = 0; remaining > 0 && fifo_idx < fifo_cnt; fifo_idx++) {
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const u32 val = ReadRegister(&this->i2c_registers->I2C_I2C_RX_FIFO_0);
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const size_t cur_bytes = std::min(remaining, sizeof(u32));
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for (size_t i = 0; i < cur_bytes; i++) {
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cur_dst[i] = static_cast<u8>((val >> (8 * i)) & 0xFF);
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}
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cur_dst += cur_bytes;
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remaining -= cur_bytes;
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}
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}
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/* N doesn't do ClearInterruptMask. */
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return ResultSuccess;
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}
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void I2cBusAccessor::SetBus(I2cBus bus) {
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this->bus = bus;
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this->i2c_registers = GetI2cRegisters(bus);
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this->clkrst_registers.SetBus(bus);
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}
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void I2cBusAccessor::CreateInterruptEvent(I2cBus bus) {
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static constexpr u64 s_interrupts[] = {
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0x46, 0x74, 0x7C, 0x98, 0x55, 0x5F
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};
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if (static_cast<size_t>(bus) >= sizeof(s_interrupts) / sizeof(s_interrupts[0])) {
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std::abort();
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}
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Handle evt_h;
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if (R_FAILED(svcCreateInterruptEvent(&evt_h, s_interrupts[static_cast<size_t>(bus)], 1))) {
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std::abort();
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}
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eventLoadRemote(&this->interrupt_event, evt_h, false);
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}
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void I2cBusAccessor::SetClock(SpeedMode speed_mode) {
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u32 t_high, t_low;
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u32 clk_div, src_div;
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u32 debounce;
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switch (speed_mode) {
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case SpeedMode_Normal:
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t_high = 2;
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t_low = 4;
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clk_div = 0x19;
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src_div = 0x13;
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debounce = 2;
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break;
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case SpeedMode_Fast:
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t_high = 2;
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t_low = 4;
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clk_div = 0x19;
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src_div = 0x04;
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debounce = 2;
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break;
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case SpeedMode_FastPlus:
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t_high = 2;
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t_low = 4;
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clk_div = 0x10;
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src_div = 0x02;
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debounce = 0;
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break;
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case SpeedMode_HighSpeed:
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t_high = 3;
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t_low = 8;
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clk_div = 0x02;
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src_div = 0x02;
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debounce = 0;
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break;
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default:
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std::abort();
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}
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if (speed_mode == SpeedMode_HighSpeed) {
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WriteRegister(&this->i2c_registers->I2C_I2C_HS_INTERFACE_TIMING_0_0, (t_high << 8) | (t_low));
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WriteRegister(&this->i2c_registers->I2C_I2C_CLK_DIVISOR_REGISTER_0, clk_div);
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} else {
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WriteRegister(&this->i2c_registers->I2C_I2C_INTERFACE_TIMING_0_0, (t_high << 8) | (t_low));
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WriteRegister(&this->i2c_registers->I2C_I2C_CLK_DIVISOR_REGISTER_0, (clk_div << 16));
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}
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WriteRegister(&this->i2c_registers->I2C_I2C_CNFG_0, debounce);
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ReadRegister(&this->i2c_registers->I2C_I2C_CNFG_0);
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if (this->pcv_module != PcvModule_I2C5) {
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if (R_FAILED(Pcv::SetReset(this->pcv_module, true))) {
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std::abort();
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}
|
||||
if (R_FAILED(Pcv::SetClockRate(this->pcv_module, (408'000'000) / (src_div + 1)))) {
|
||||
std::abort();
|
||||
}
|
||||
if (R_FAILED(Pcv::SetReset(this->pcv_module, false))) {
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void I2cBusAccessor::ResetController() const {
|
||||
if (this->pcv_module != PcvModule_I2C5) {
|
||||
if (R_FAILED(Pcv::SetReset(this->pcv_module, true))) {
|
||||
std::abort();
|
||||
}
|
||||
if (R_FAILED(Pcv::SetClockRate(this->pcv_module, 81'600'000))) {
|
||||
std::abort();
|
||||
}
|
||||
if (R_FAILED(Pcv::SetReset(this->pcv_module, false))) {
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void I2cBusAccessor::ClearBus() const {
|
||||
bool success = false;
|
||||
for (size_t i = 0; i < 3 && !success; i++) {
|
||||
success = true;
|
||||
|
||||
this->ResetController();
|
||||
|
||||
WriteRegister(&this->i2c_registers->I2C_I2C_BUS_CLEAR_CONFIG_0, 0x90000);
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_BUS_CLEAR_CONFIG_0, 0x4);
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_BUS_CLEAR_CONFIG_0, 0x2);
|
||||
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_CONFIG_LOAD_0, 0x1);
|
||||
{
|
||||
u64 start_tick = armGetSystemTick();
|
||||
while (ReadRegister(&this->i2c_registers->I2C_I2C_CONFIG_LOAD_0) & 1) {
|
||||
if (armTicksToNs(armGetSystemTick() - start_tick) > 1'000'000) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (!success) {
|
||||
continue;
|
||||
}
|
||||
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_BUS_CLEAR_CONFIG_0, 0x1);
|
||||
{
|
||||
u64 start_tick = armGetSystemTick();
|
||||
while (ReadRegister(&this->i2c_registers->I2C_I2C_BUS_CLEAR_CONFIG_0) & 1) {
|
||||
if (armTicksToNs(armGetSystemTick() - start_tick) > 1'000'000) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (!success) {
|
||||
continue;
|
||||
}
|
||||
|
||||
{
|
||||
u64 start_tick = armGetSystemTick();
|
||||
while (ReadRegister(&this->i2c_registers->I2C_I2C_BUS_CLEAR_STATUS_0) & 1) {
|
||||
if (armTicksToNs(armGetSystemTick() - start_tick) > 1'000'000) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (!success) {
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void I2cBusAccessor::DisableClock() {
|
||||
if (R_FAILED(Pcv::SetClockEnabled(this->pcv_module, false))) {
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
|
||||
void I2cBusAccessor::SetPacketMode() {
|
||||
/* Set PACKET_MODE_EN, MSTR_CONFIG_LOAD */
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_CNFG_0, 0x400);
|
||||
SetRegisterBits(&this->i2c_registers->I2C_I2C_CONFIG_LOAD_0, 0x1);
|
||||
|
||||
/* Set TX_FIFO_TRIGGER, RX_FIFO_TRIGGER */
|
||||
WriteRegister(&this->i2c_registers->I2C_FIFO_CONTROL_0, 0xFC);
|
||||
}
|
||||
|
||||
Result I2cBusAccessor::FlushFifos() {
|
||||
WriteRegister(&this->i2c_registers->I2C_FIFO_CONTROL_0, 0xFF);
|
||||
|
||||
/* Wait for flush to finish, check every ms for 5 ms. */
|
||||
for (size_t i = 0; i < 5; i++) {
|
||||
if (!(ReadRegister(&this->i2c_registers->I2C_FIFO_CONTROL_0) & 3)) {
|
||||
return ResultSuccess;
|
||||
}
|
||||
svcSleepThread(1'000'000ul);
|
||||
}
|
||||
|
||||
return ResultI2cBusBusy;
|
||||
}
|
||||
|
||||
Result I2cBusAccessor::GetTransactionResult() const {
|
||||
const u32 packet_status = ReadRegister(&this->i2c_registers->I2C_PACKET_TRANSFER_STATUS_0);
|
||||
const u32 interrupt_status = ReadRegister(&this->i2c_registers->I2C_INTERRUPT_STATUS_REGISTER_0);
|
||||
|
||||
/* Check for no ack. */
|
||||
if ((packet_status & 0xC) || (interrupt_status & 0x8)) {
|
||||
return ResultI2cNoAck;
|
||||
}
|
||||
|
||||
/* Check for arb lost. */
|
||||
if ((packet_status & 0x2) || (interrupt_status & 0x4)) {
|
||||
this->ClearBus();
|
||||
return ResultI2cBusBusy;
|
||||
}
|
||||
|
||||
return ResultSuccess;
|
||||
}
|
||||
|
||||
void I2cBusAccessor::HandleTransactionResult(Result result) {
|
||||
if (R_FAILED(result)) {
|
||||
if (result == ResultI2cNoAck || result == ResultI2cBusBusy) {
|
||||
this->ResetController();
|
||||
this->SetClock(this->speed_mode);
|
||||
this->SetPacketMode();
|
||||
this->FlushFifos();
|
||||
} else {
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Result I2cBusAccessor::GetAndHandleTransactionResult() {
|
||||
Result rc = this->GetTransactionResult();
|
||||
this->HandleTransactionResult(rc);
|
||||
|
||||
if (R_FAILED(rc)) {
|
||||
this->ClearInterruptMask();
|
||||
eventClear(&this->interrupt_event);
|
||||
return rc;
|
||||
}
|
||||
return ResultSuccess;
|
||||
}
|
||||
|
||||
void I2cBusAccessor::WriteTransferHeader(TransferMode transfer_mode, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address, size_t num_bytes) {
|
||||
this->FlushFifos();
|
||||
|
||||
WriteRegister(&this->i2c_registers->I2C_I2C_TX_PACKET_FIFO_0, 0x10);
|
||||
WriteRegister(&this->i2c_registers->I2C_I2C_TX_PACKET_FIFO_0, static_cast<u32>(num_bytes - 1) & 0xFFF);
|
||||
|
||||
const u32 slave_addr_val = ((transfer_mode == TransferMode_Receive) & 1) | ((slave_address & 0x7F) << 1);
|
||||
u32 hdr_val = 0;
|
||||
hdr_val |= ((this->speed_mode == SpeedMode_HighSpeed) & 1) << 22;
|
||||
hdr_val |= ((transfer_mode == TransferMode_Receive) & 1) << 19;
|
||||
hdr_val |= ((addressing_mode != AddressingMode_7Bit) & 1) << 18;
|
||||
hdr_val |= (1 << 17);
|
||||
hdr_val |= (((option & I2cTransactionOption_Stop) != 0) & 1) << 18;
|
||||
hdr_val |= slave_addr_val;
|
||||
|
||||
WriteRegister(&this->i2c_registers->I2C_I2C_TX_PACKET_FIFO_0, hdr_val);
|
||||
}
|
||||
79
stratosphere/boot/source/i2c_driver/i2c_bus_accessor.hpp
Normal file
79
stratosphere/boot/source/i2c_driver/i2c_bus_accessor.hpp
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <switch.h>
|
||||
#include <stratosphere.hpp>
|
||||
|
||||
#include "i2c_types.hpp"
|
||||
#include "i2c_registers.hpp"
|
||||
|
||||
class I2cBusAccessor {
|
||||
private:
|
||||
enum TransferMode {
|
||||
TransferMode_Send = 0,
|
||||
TransferMode_Receive = 1,
|
||||
};
|
||||
static constexpr u64 InterruptTimeout = 100'000'000ul;
|
||||
private:
|
||||
Event interrupt_event;
|
||||
HosMutex open_mutex;
|
||||
HosMutex register_mutex;
|
||||
I2cRegisters *i2c_registers = nullptr;
|
||||
ClkRstRegisters clkrst_registers;
|
||||
SpeedMode speed_mode = SpeedMode_Fast;
|
||||
size_t open_sessions = 0;
|
||||
I2cBus bus = I2cBus_I2c1;
|
||||
PcvModule pcv_module = PcvModule_I2C1;
|
||||
bool suspended = false;
|
||||
public:
|
||||
I2cBusAccessor() {
|
||||
/* ... */
|
||||
}
|
||||
private:
|
||||
inline void ClearInterruptMask() const {
|
||||
WriteRegister(&i2c_registers->I2C_INTERRUPT_MASK_REGISTER_0, 0);
|
||||
ReadRegister(&i2c_registers->I2C_INTERRUPT_MASK_REGISTER_0);
|
||||
}
|
||||
|
||||
void SetBus(I2cBus bus);
|
||||
void CreateInterruptEvent(I2cBus bus);
|
||||
void SetClock(SpeedMode speed_mode);
|
||||
|
||||
void ResetController() const;
|
||||
void ClearBus() const;
|
||||
void DisableClock();
|
||||
void SetPacketMode();
|
||||
Result FlushFifos();
|
||||
|
||||
Result GetTransactionResult() const;
|
||||
void HandleTransactionResult(Result result);
|
||||
Result GetAndHandleTransactionResult();
|
||||
|
||||
void WriteTransferHeader(TransferMode transfer_mode, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address, size_t num_bytes);
|
||||
public:
|
||||
void Open(I2cBus bus, SpeedMode speed_mode);
|
||||
void Close();
|
||||
void Suspend();
|
||||
void Resume();
|
||||
void DoInitialConfig();
|
||||
|
||||
size_t GetOpenSessions() const;
|
||||
bool GetBusy() const;
|
||||
|
||||
Result Send(const u8 *data, size_t num_bytes, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address);
|
||||
Result Receive(u8 *out_data, size_t num_bytes, I2cTransactionOption option, AddressingMode addressing_mode, u32 slave_address);
|
||||
};
|
||||
|
|
@ -114,4 +114,4 @@ u64 GetI2cDeviceRetryWaitTime(I2cDevice dev) {
|
|||
const size_t dev_idx = GetI2cDeviceIndex(dev);
|
||||
if (dev_idx == I2cDeviceInvalidIndex) { std::abort(); }
|
||||
return g_device_configs[dev_idx].retry_wait_time;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
141
stratosphere/boot/source/i2c_driver/i2c_registers.hpp
Normal file
141
stratosphere/boot/source/i2c_driver/i2c_registers.hpp
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <switch.h>
|
||||
#include <stratosphere.hpp>
|
||||
|
||||
#include "i2c_types.hpp"
|
||||
|
||||
static inline uintptr_t GetIoMapping(u64 io_addr, u64 io_size) {
|
||||
u64 vaddr;
|
||||
u64 aligned_addr = (io_addr & ~0xFFFul);
|
||||
u64 aligned_size = io_size + (io_addr - aligned_addr);
|
||||
if (R_FAILED(svcQueryIoMapping(&vaddr, aligned_addr, aligned_size))) {
|
||||
std::abort();
|
||||
}
|
||||
return static_cast<uintptr_t>(vaddr + (io_addr - aligned_addr));
|
||||
}
|
||||
|
||||
struct I2cRegisters {
|
||||
volatile u32 I2C_I2C_CNFG_0;
|
||||
volatile u32 I2C_I2C_CMD_ADDR0_0;
|
||||
volatile u32 I2C_I2C_CMD_ADDR1_0;
|
||||
volatile u32 I2C_I2C_CMD_DATA1_0;
|
||||
volatile u32 I2C_I2C_CMD_DATA2_0;
|
||||
volatile u32 _0x14;
|
||||
volatile u32 _0x18;
|
||||
volatile u32 I2C_I2C_STATUS_0;
|
||||
volatile u32 I2C_I2C_SL_CNFG_0;
|
||||
volatile u32 I2C_I2C_SL_RCVD_0;
|
||||
volatile u32 I2C_I2C_SL_STATUS_0;
|
||||
volatile u32 I2C_I2C_SL_ADDR1_0;
|
||||
volatile u32 I2C_I2C_SL_ADDR2_0;
|
||||
volatile u32 I2C_I2C_TLOW_SEXT_0;
|
||||
volatile u32 _0x38;
|
||||
volatile u32 I2C_I2C_SL_DELAY_COUNT_0;
|
||||
volatile u32 I2C_I2C_SL_INT_MASK_0;
|
||||
volatile u32 I2C_I2C_SL_INT_SOURCE_0;
|
||||
volatile u32 I2C_I2C_SL_INT_SET_0;
|
||||
volatile u32 _0x4C;
|
||||
volatile u32 I2C_I2C_TX_PACKET_FIFO_0;
|
||||
volatile u32 I2C_I2C_RX_FIFO_0;
|
||||
volatile u32 I2C_PACKET_TRANSFER_STATUS_0;
|
||||
volatile u32 I2C_FIFO_CONTROL_0;
|
||||
volatile u32 I2C_FIFO_STATUS_0;
|
||||
volatile u32 I2C_INTERRUPT_MASK_REGISTER_0;
|
||||
volatile u32 I2C_INTERRUPT_STATUS_REGISTER_0;
|
||||
volatile u32 I2C_I2C_CLK_DIVISOR_REGISTER_0;
|
||||
volatile u32 I2C_I2C_INTERRUPT_SOURCE_REGISTER_0;
|
||||
volatile u32 I2C_I2C_INTERRUPT_SET_REGISTER_0;
|
||||
volatile u32 I2C_I2C_SLV_TX_PACKET_FIFO_0;
|
||||
volatile u32 I2C_I2C_SLV_RX_FIFO_0;
|
||||
volatile u32 I2C_I2C_SLV_PACKET_STATUS_0;
|
||||
volatile u32 I2C_I2C_BUS_CLEAR_CONFIG_0;
|
||||
volatile u32 I2C_I2C_BUS_CLEAR_STATUS_0;
|
||||
volatile u32 I2C_I2C_CONFIG_LOAD_0;
|
||||
volatile u32 _0x90;
|
||||
volatile u32 I2C_I2C_INTERFACE_TIMING_0_0;
|
||||
volatile u32 I2C_I2C_INTERFACE_TIMING_1_0;
|
||||
volatile u32 I2C_I2C_HS_INTERFACE_TIMING_0_0;
|
||||
volatile u32 I2C_I2C_HS_INTERFACE_TIMING_1_0;
|
||||
};
|
||||
|
||||
static inline I2cRegisters *GetI2cRegisters(I2cBus bus) {
|
||||
static constexpr uintptr_t s_offsets[] = {
|
||||
0x0000, 0x0400, 0x0500, 0x0700, 0x1000, 0x1100
|
||||
};
|
||||
if (bus >= sizeof(s_offsets) / sizeof(s_offsets[0])) {
|
||||
std::abort();
|
||||
}
|
||||
|
||||
const uintptr_t registers = GetIoMapping(0x7000c000ul, 0x2000) + s_offsets[static_cast<size_t>(bus)];
|
||||
return reinterpret_cast<I2cRegisters *>(registers);
|
||||
}
|
||||
|
||||
struct ClkRstRegisters {
|
||||
public:
|
||||
volatile u32 *clk_src_reg;
|
||||
volatile u32 *clk_en_reg;
|
||||
volatile u32 *rst_reg;
|
||||
u32 mask;
|
||||
public:
|
||||
void SetBus(I2cBus bus) {
|
||||
static constexpr uintptr_t s_clk_src_offsets[] = {
|
||||
0x124, 0x198, 0x1b8, 0x3c4, 0x128, 0x65c
|
||||
};
|
||||
static constexpr uintptr_t s_clk_en_offsets[] = {
|
||||
0x010, 0x014, 0x018, 0x360, 0x014, 0x280
|
||||
};
|
||||
static constexpr uintptr_t s_rst_offsets[] = {
|
||||
0x004, 0x008, 0x00c, 0x358, 0x008, 0x28c
|
||||
};
|
||||
static constexpr size_t s_bit_shifts[] = {
|
||||
12, 22, 3, 7, 15, 6
|
||||
};
|
||||
if (bus >= sizeof(s_clk_src_offsets) / sizeof(s_clk_src_offsets[0])) {
|
||||
std::abort();
|
||||
}
|
||||
|
||||
const uintptr_t registers = GetIoMapping(0x60006000ul, 0x1000);
|
||||
const size_t idx = static_cast<size_t>(bus);
|
||||
this->clk_src_reg = reinterpret_cast<volatile u32 *>(registers + s_clk_src_offsets[idx]);
|
||||
this->clk_en_reg = reinterpret_cast<volatile u32 *>(registers + s_clk_en_offsets[idx]);
|
||||
this->rst_reg = reinterpret_cast<volatile u32 *>(registers + s_rst_offsets[idx]);
|
||||
this->mask = (1u << s_bit_shifts[idx]);
|
||||
}
|
||||
};
|
||||
|
||||
static inline void WriteRegister(volatile u32 *reg, u32 val) {
|
||||
*reg = val;
|
||||
}
|
||||
|
||||
static inline u32 ReadRegister(volatile u32 *reg) {
|
||||
u32 val = *reg;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void SetRegisterBits(volatile u32 *reg, u32 mask) {
|
||||
*reg |= mask;
|
||||
}
|
||||
|
||||
static inline void ClearRegisterBits(volatile u32 *reg, u32 mask) {
|
||||
*reg &= mask;
|
||||
}
|
||||
|
||||
static inline void ReadWriteRegisterBits(volatile u32 *reg, u32 val, u32 mask) {
|
||||
*reg = (*reg & (~mask)) | (val & mask);
|
||||
}
|
||||
|
|
@ -1 +1 @@
|
|||
Subproject commit a1890715371cd3e171130d951907f1afb11b08b8
|
||||
Subproject commit c3d344cd1bbad9e759732f866db59a84e4f86357
|
||||
Loading…
Reference in a new issue