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Code Issues Releases Activity

fusee: accurately match Mariko pk1ldr

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This commit is contained in:
hexkyz 2020-12-06 19:08:07 +00:00 committed by Michael Scire
parent 0a0cc52846
commit 4d4fc19cba
7 changed files with 169 additions and 157 deletions
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38
fusee/fusee-mtc/src/car.h
View file

@ -37,23 +37,27 @@
/* Clock and reset devices. */ /* Clock and reset devices. */
typedef enum { typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6), CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTB = ((0 << 5) | 0x7), CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTC = ((1 << 5) | 0x17), CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC), CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF), CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E), CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_SE = ((3 << 5) | 0x1F), CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C), CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_TSEC = ((2 << 5) | 0x13), CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_SOR0 = ((5 << 5) | 0x16), CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_SOR1 = ((5 << 5) | 0x17), CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17), CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_BPMP = ((0 << 5) | 0x1) CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice; } CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -283,7 +287,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c; uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */ /* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set; uint32_t rst_dev_v_set;

38
fusee/fusee-primary/fusee-primary-main/src/car.h
View file

@ -37,23 +37,27 @@
/* Clock and reset devices. */ /* Clock and reset devices. */
typedef enum { typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6), CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTB = ((0 << 5) | 0x7), CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTC = ((1 << 5) | 0x17), CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC), CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF), CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E), CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_SE = ((3 << 5) | 0x1F), CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C), CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_TSEC = ((2 << 5) | 0x13), CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_SOR0 = ((5 << 5) | 0x16), CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_SOR1 = ((5 << 5) | 0x17), CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17), CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_BPMP = ((0 << 5) | 0x1) CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice; } CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -283,7 +287,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c; uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */ /* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set; uint32_t rst_dev_v_set;

10
fusee/fusee-primary/fusee-primary-main/src/hwinit.c
View file

@ -335,14 +335,12 @@ static void nx_hwinit_mariko(bool enable_log) {
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_car_t *car = car_get_regs(); volatile tegra_car_t *car = car_get_regs();
/* Enable SE clock. */ /* Enable SE clock and lock it. */
clkrst_reboot(CARDEVICE_SE); clkrst_reboot(CARDEVICE_SE);
car->clk_source_se |= 0x100;
/* Initialize the fuse driver. */ /* Make all fuse registers visible. */
fuse_init(); clkrst_enable_fuse_regs(true);
/* Initialize the memory controller. */
mc_enable();
/* Configure oscillators. */ /* Configure oscillators. */
config_oscillators(); config_oscillators();

2
fusee/fusee-secondary/src/car.h
View file

@ -287,7 +287,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c; uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */ /* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set; uint32_t rst_dev_v_set;

38
sept/sept-primary/src/car.h
View file

@ -37,23 +37,27 @@
/* Clock and reset devices. */ /* Clock and reset devices. */
typedef enum { typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6), CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTB = ((0 << 5) | 0x7), CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTC = ((1 << 5) | 0x17), CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC), CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF), CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E), CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_SE = ((3 << 5) | 0x1F), CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C), CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_TSEC = ((2 << 5) | 0x13), CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_SOR0 = ((5 << 5) | 0x16), CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_SOR1 = ((5 << 5) | 0x17), CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17), CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_BPMP = ((0 << 5) | 0x1) CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice; } CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -283,7 +287,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c; uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */ /* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set; uint32_t rst_dev_v_set;

38
sept/sept-secondary/src/car.h
View file

@ -37,23 +37,27 @@
/* Clock and reset devices. */ /* Clock and reset devices. */
typedef enum { typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6), CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTB = ((0 << 5) | 0x7), CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTC = ((1 << 5) | 0x17), CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC), CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF), CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E), CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_SE = ((3 << 5) | 0x1F), CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C), CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_TSEC = ((2 << 5) | 0x13), CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_SOR0 = ((5 << 5) | 0x16), CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_SOR1 = ((5 << 5) | 0x17), CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17), CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_BPMP = ((0 << 5) | 0x1) CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice; } CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -283,7 +287,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c; uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */ /* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set; uint32_t rst_dev_v_set;

10
sept/sept-secondary/src/hwinit.c
View file

@ -335,14 +335,12 @@ static void nx_hwinit_mariko(bool enable_log) {
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_car_t *car = car_get_regs(); volatile tegra_car_t *car = car_get_regs();
/* Enable SE clock. */ /* Enable SE clock and lock it. */
clkrst_reboot(CARDEVICE_SE); clkrst_reboot(CARDEVICE_SE);
car->clk_source_se |= 0x100;
/* Initialize the fuse driver. */ /* Make all fuse registers visible. */
fuse_init(); clkrst_enable_fuse_regs(true);
/* Initialize the memory controller. */
mc_enable();
/* Configure oscillators. */ /* Configure oscillators. */
config_oscillators(); config_oscillators();