From 570989384b9edd2489175db59fc2d6bc0c89ca3e Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Thu, 10 Oct 2024 16:10:18 -0700 Subject: [PATCH] kern: first round of page table refactor bug fixes --- .../libmesosphere/source/arch/arm64/kern_k_page_table.cpp | 4 ++-- .../source/arch/arm64/kern_k_page_table_impl.cpp | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/libraries/libmesosphere/source/arch/arm64/kern_k_page_table.cpp b/libraries/libmesosphere/source/arch/arm64/kern_k_page_table.cpp index cbd586289..d488a1152 100644 --- a/libraries/libmesosphere/source/arch/arm64/kern_k_page_table.cpp +++ b/libraries/libmesosphere/source/arch/arm64/kern_k_page_table.cpp @@ -540,7 +540,7 @@ namespace ams::kern::arch::arm64 { const size_t num_ptes = cur_pages / (block_size / PageSize); auto *pte = context.level_entries[context.level]; for (size_t i = 0; i < num_ptes; ++i) { - *pte = PageTableEntry(PageTableEntry::BlockTag{}, phys_addr + i * block_size, entry_template, sw_reserved_bits, contig, context.level == KPageTableImpl::EntryLevel_L3); + pte[i] = PageTableEntry(PageTableEntry::BlockTag{}, phys_addr + i * block_size, entry_template, sw_reserved_bits, contig, context.level == KPageTableImpl::EntryLevel_L3); sw_reserved_bits &= ~(PageTableEntry::SoftwareReservedBit_DisableMergeHead); } @@ -803,7 +803,7 @@ namespace ams::kern::arch::arm64 { } /* Separate. */ - impl.SeparatePages(entry, context, virt_addr, nullptr); + impl.SeparatePages(entry, context, virt_addr, GetPointer(table)); this->NoteUpdated(); } diff --git a/libraries/libmesosphere/source/arch/arm64/kern_k_page_table_impl.cpp b/libraries/libmesosphere/source/arch/arm64/kern_k_page_table_impl.cpp index 249024a29..3a9c1275b 100644 --- a/libraries/libmesosphere/source/arch/arm64/kern_k_page_table_impl.cpp +++ b/libraries/libmesosphere/source/arch/arm64/kern_k_page_table_impl.cpp @@ -261,7 +261,7 @@ namespace ams::kern::arch::arm64 { auto * const first = context->level_entries[context->level]; const KPhysicalAddress block = this->GetBlock(first, context->level); for (size_t i = 0; i < BlocksPerTable; ++i) { - pte[i] = PageTableEntry(PageTableEntry::BlockTag{}, block + (i << (PageBits + LevelBits * (context->level - 1))), PageTableEntry(first->GetEntryTemplateForSeparate(i)), PageTableEntry::SoftwareReservedBit_None, true, context->level == EntryLevel_L3); + pte[i] = PageTableEntry(PageTableEntry::BlockTag{}, block + (i << (PageBits + LevelBits * (context->level - 1))), PageTableEntry(first->GetEntryTemplateForSeparate(i)), PageTableEntry::SoftwareReservedBit_None, true, context->level - 1 == EntryLevel_L3); } context->is_contiguous = true; @@ -271,7 +271,8 @@ namespace ams::kern::arch::arm64 { cpu::DataSynchronizationBarrierInnerShareableStore(); /* Update the block entry to be a table entry. */ - *context->level_entries[context->level + 1] = PageTableEntry(PageTableEntry::TableTag{}, KPageTable::GetPageTablePhysicalAddress(KVirtualAddress(first)), m_is_kernel, true, BlocksPerTable); + *context->level_entries[context->level + 1] = PageTableEntry(PageTableEntry::TableTag{}, KPageTable::GetPageTablePhysicalAddress(KVirtualAddress(pte)), m_is_kernel, true, BlocksPerTable); + context->level_entries[context->level] = pte + this->GetLevelIndex(address, context->level); }