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https://github.com/Atmosphere-NX/Atmosphere.git
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dmnt-cheat: Add register conditional vm instruction
This commit is contained in:
Michael Scire
parent
e5ecd243f2
commit
5d79952bdd
2 changed files with 184 additions and 1 deletions
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@ -144,6 +144,37 @@ void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
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break;
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}
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break;
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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this->LogToDebugFile("Opcode: Begin Register Conditional\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->begin_reg_cond.bit_width);
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this->LogToDebugFile("V Reg Idx: %x\n", opcode->begin_reg_cond.val_reg_index);
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switch (opcode->begin_reg_cond.comp_type) {
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case CompareRegisterValueType_StaticValue:
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this->LogToDebugFile("Comp Type: Static Value\n");
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this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64);
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break;
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case CompareRegisterValueType_MemoryRelAddr:
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this->LogToDebugFile("Comp Type: Memory Relative Address\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_MemoryOfsReg:
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this->LogToDebugFile("Comp Type: Memory Offset Register\n");
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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case CompareRegisterValueType_RegisterRelAddr:
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this->LogToDebugFile("Comp Type: Register Relative Address\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_RegisterOfsReg:
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this->LogToDebugFile("Comp Type: Register Offset Register\n");
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this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
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break;
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}
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break;
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default:
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this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode);
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break;
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@ -208,6 +239,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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switch (opcode.opcode) {
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case CheatVmOpcodeType_BeginConditionalBlock:
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case CheatVmOpcodeType_BeginKeypressConditionalBlock:
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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opcode.begin_conditional_block = true;
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break;
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default:
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@ -356,6 +388,52 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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}
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}
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break;
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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{
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/* C0TcSX## */
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/* C0TcS0Ma aaaaaaaa */
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/* C0TcS1Mr */
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/* C0TcS2Ra aaaaaaaa */
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/* C0TcS3Rr */
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/* C0TcS400 VVVVVVVV (VVVVVVVV) */
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/* C0 = opcode 0xC0 */
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/* T = bit width */
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/* c = condition type. */
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/* S = source register. */
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/* X = value operand type, 0 = main/heap with relative offset, 1 = main/heap with offset register, */
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/* 1 = register with relative offset, 2 = register with offset register, 3 = static value. */
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/* M = memory type. */
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/* a = relative address. */
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/* r = offset register. */
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/* V = value */
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opcode.begin_reg_cond.bit_width = (first_dword >> 20) & 0xF;
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opcode.begin_reg_cond.cond_type = (ConditionalComparisonType)((first_dword >> 16) & 0xF);
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opcode.begin_reg_cond.val_reg_index = ((first_dword >> 12) & 0xF);
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opcode.begin_reg_cond.comp_type = (CompareRegisterValueType)((first_dword >> 8) & 0xF);
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switch (opcode.begin_reg_cond.comp_type) {
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case CompareRegisterValueType_StaticValue:
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opcode.begin_reg_cond.value = GetNextVmInt(opcode.begin_reg_cond.bit_width);
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break;
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case CompareRegisterValueType_MemoryRelAddr:
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opcode.begin_reg_cond.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
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opcode.begin_reg_cond.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
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break;
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case CompareRegisterValueType_MemoryOfsReg:
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opcode.begin_reg_cond.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
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opcode.begin_reg_cond.ofs_reg_index = (first_dword & 0xF);
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break;
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case CompareRegisterValueType_RegisterRelAddr:
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opcode.begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF);
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opcode.begin_reg_cond.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
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break;
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case CompareRegisterValueType_RegisterOfsReg:
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opcode.begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF);
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opcode.begin_reg_cond.ofs_reg_index = (first_dword & 0xF);
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break;
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}
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}
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break;
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case CheatVmOpcodeType_ExtendedWidth:
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default:
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/* Unrecognized instruction cannot be decoded. */
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@ -754,6 +832,86 @@ void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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}
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}
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break;
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case CheatVmOpcodeType_BeginRegisterConditionalBlock:
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{
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/* Get value from register. */
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u64 src_value = 0;
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switch (cur_opcode.begin_reg_cond.bit_width) {
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case 1:
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src_value = static_cast<u8>(this->registers[cur_opcode.begin_reg_cond.val_reg_index] & 0xFFul);
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break;
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case 2:
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src_value = static_cast<u16>(this->registers[cur_opcode.begin_reg_cond.val_reg_index] & 0xFFFFul);
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break;
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case 4:
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src_value = static_cast<u32>(this->registers[cur_opcode.begin_reg_cond.val_reg_index] & 0xFFFFFFFFul);
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break;
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case 8:
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src_value = static_cast<u64>(this->registers[cur_opcode.begin_reg_cond.val_reg_index] & 0xFFFFFFFFFFFFFFFFul);
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break;
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}
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/* Read value from memory. */
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u64 cond_value = 0;
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if (cur_opcode.begin_reg_cond.comp_type == CompareRegisterValueType_StaticValue) {
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cond_value = GetVmInt(cur_opcode.begin_reg_cond.value, cur_opcode.begin_reg_cond.bit_width);
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} else {
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u64 cond_address = 0;
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switch (cur_opcode.begin_reg_cond.comp_type) {
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case CompareRegisterValueType_MemoryRelAddr:
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cond_address = GetCheatProcessAddress(metadata, cur_opcode.begin_reg_cond.mem_type, cur_opcode.begin_reg_cond.rel_address);
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break;
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case CompareRegisterValueType_MemoryOfsReg:
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cond_address = GetCheatProcessAddress(metadata, cur_opcode.begin_reg_cond.mem_type, this->registers[cur_opcode.begin_reg_cond.ofs_reg_index]);
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break;
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case CompareRegisterValueType_RegisterRelAddr:
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cond_address = this->registers[cur_opcode.begin_reg_cond.addr_reg_index] + cur_opcode.begin_reg_cond.rel_address;
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break;
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case CompareRegisterValueType_RegisterOfsReg:
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cond_address = this->registers[cur_opcode.begin_reg_cond.addr_reg_index] + this->registers[cur_opcode.begin_reg_cond.ofs_reg_index];
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break;
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default:
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break;
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}
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switch (cur_opcode.begin_reg_cond.bit_width) {
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case 1:
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case 2:
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case 4:
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case 8:
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DmntCheatManager::ReadCheatProcessMemoryForVm(cond_address, &cond_value, cur_opcode.begin_reg_cond.bit_width);
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break;
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}
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}
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/* Check against condition. */
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bool cond_met = false;
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switch (cur_opcode.begin_reg_cond.cond_type) {
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case ConditionalComparisonType_GT:
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cond_met = src_value > cond_value;
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break;
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case ConditionalComparisonType_GE:
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cond_met = src_value >= cond_value;
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break;
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case ConditionalComparisonType_LT:
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cond_met = src_value < cond_value;
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break;
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case ConditionalComparisonType_LE:
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cond_met = src_value <= cond_value;
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break;
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case ConditionalComparisonType_EQ:
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cond_met = src_value == cond_value;
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break;
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case ConditionalComparisonType_NE:
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cond_met = src_value != cond_value;
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break;
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}
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/* Skip conditional block if condition not met. */
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if (!cond_met) {
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this->SkipConditionalBlock();
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}
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}
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break;
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default:
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/* By default, we do a no-op. */
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break;
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@ -35,10 +35,14 @@ enum CheatVmOpcodeType : u32 {
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/* These are not implemented by Gateway's VM. */
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CheatVmOpcodeType_PerformArithmeticRegister = 9,
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CheatVmOpcodeType_StoreRegisterToAddress = 10,
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CheatVmOpcodeType_Reserved11 = 11,
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/* This is a meta entry, and not a real opcode. */
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/* This is to facilitate multi-nybble instruction decoding in the future. */
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/* This is to facilitate multi-nybble instruction decoding. */
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CheatVmOpcodeType_ExtendedWidth = 12,
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/* Extended width opcodes. */
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CheatVmOpcodeType_BeginRegisterConditionalBlock = 0xC0,
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};
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enum MemoryAccessType : u32 {
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@ -77,6 +81,14 @@ enum StoreRegisterOffsetType : u32 {
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StoreRegisterOffsetType_Imm = 2,
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};
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enum CompareRegisterValueType : u32 {
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CompareRegisterValueType_MemoryRelAddr = 0,
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CompareRegisterValueType_MemoryOfsReg = 1,
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CompareRegisterValueType_RegisterRelAddr = 2,
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CompareRegisterValueType_RegisterOfsReg = 3,
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CompareRegisterValueType_StaticValue = 4,
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};
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union VmInt {
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u8 bit8;
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u16 bit16;
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@ -161,6 +173,18 @@ struct StoreRegisterToAddressOpcode {
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u64 rel_address;
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};
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struct BeginRegisterConditionalOpcode {
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u32 bit_width;
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ConditionalComparisonType cond_type;
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u32 val_reg_index;
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CompareRegisterValueType comp_type;
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MemoryAccessType mem_type;
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u32 addr_reg_index;
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u32 ofs_reg_index;
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u64 rel_address;
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VmInt value;
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};
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struct CheatVmOpcode {
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CheatVmOpcodeType opcode;
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@ -177,6 +201,7 @@ struct CheatVmOpcode {
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BeginKeypressConditionalOpcode begin_keypress_cond;
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PerformArithmeticRegisterOpcode perform_math_reg;
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StoreRegisterToAddressOpcode str_register;
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BeginRegisterConditionalOpcode begin_reg_cond;
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};
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};
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