mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-09 21:51:45 +00:00
warmboot: Add device debug configuration
This commit is contained in:
Michael Scire
parent
e0f1e637f7
commit
5f905c6b42
6 changed files with 320 additions and 1 deletions
189
exosphere/lp0fw/src/fuse.h
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189
exosphere/lp0fw/src/fuse.h
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/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_WARMBOOT_BIN_FUSE_H
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#define EXOSPHERE_WARMBOOT_BIN_FUSE_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "utils.h"
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typedef struct {
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uint32_t FUSE_CTRL;
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uint32_t FUSE_REG_ADDR;
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uint32_t FUSE_REG_READ;
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uint32_t FUSE_REG_WRITE;
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uint32_t FUSE_TIME_RD1;
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uint32_t FUSE_TIME_RD2;
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uint32_t FUSE_TIME_PGM1;
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uint32_t FUSE_TIME_PGM2;
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uint32_t FUSE_PRIV2INTFC;
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uint32_t FUSE_FUSEBYPASS;
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uint32_t FUSE_PRIVATEKEYDISABLE;
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uint32_t FUSE_DIS_PGM;
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uint32_t FUSE_WRITE_ACCESS;
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uint32_t FUSE_PWR_GOOD_SW;
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uint32_t _0x38[0x32];
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} fuse_registers_t;
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typedef struct {
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t _0x4;
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uint32_t _0x8;
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uint32_t _0xC;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0;
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uint32_t FUSE_CPU_IDDQ;
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uint32_t _0x1C;
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uint32_t _0x20;
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uint32_t _0x24;
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uint32_t FUSE_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1;
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uint32_t FUSE_CPU_SPEEDO_2;
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uint32_t FUSE_SOC_SPEEDO_0;
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uint32_t FUSE_SOC_SPEEDO_1;
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uint32_t FUSE_SOC_SPEEDO_2;
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uint32_t FUSE_SOC_IDDQ;
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uint32_t _0x44;
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uint32_t FUSE_FA;
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uint32_t _0x4C;
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uint32_t _0x50;
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uint32_t _0x54;
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uint32_t _0x58;
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uint32_t _0x5C;
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uint32_t _0x60;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR_1;
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uint32_t FUSE_TSENSOR_2;
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uint32_t _0x8C;
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uint32_t FUSE_CP_REV;
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uint32_t _0x94;
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uint32_t FUSE_TSENSOR_0;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE_REG;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x4];
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uint32_t FUSE_DEVICE_KEY;
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uint32_t _0xB8;
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uint32_t _0xBC;
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uint32_t FUSE_RESERVED_SW;
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uint32_t FUSE_VP8_ENABLE;
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uint32_t FUSE_RESERVED_ODM[0x8];
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uint32_t _0xE8;
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uint32_t _0xEC;
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uint32_t FUSE_SKU_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t _0xF8;
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uint32_t _0xFC;
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uint32_t FUSE_VENDOR_CODE;
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uint32_t FUSE_FAB_CODE;
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uint32_t FUSE_LOT_CODE_0;
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uint32_t FUSE_LOT_CODE_1;
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uint32_t FUSE_WAFER_ID;
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uint32_t FUSE_X_COORDINATE;
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uint32_t FUSE_Y_COORDINATE;
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uint32_t _0x11C;
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uint32_t _0x120;
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uint32_t FUSE_SATA_CALIB;
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uint32_t FUSE_GPU_IDDQ;
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uint32_t FUSE_TSENSOR_3;
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uint32_t _0x130;
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uint32_t _0x134;
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uint32_t _0x138;
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uint32_t _0x13C;
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uint32_t _0x140;
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uint32_t _0x144;
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uint32_t FUSE_OPT_SUBREVISION;
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uint32_t _0x14C;
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uint32_t _0x150;
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uint32_t FUSE_TSENSOR_4;
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uint32_t FUSE_TSENSOR_5;
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uint32_t FUSE_TSENSOR_6;
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uint32_t FUSE_TSENSOR_7;
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uint32_t FUSE_OPT_PRIV_SEC_DIS;
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uint32_t FUSE_PKC_DISABLE;
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uint32_t _0x16C;
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uint32_t _0x170;
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uint32_t _0x174;
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uint32_t _0x178;
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uint32_t _0x17C;
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uint32_t FUSE_TSENSOR_COMMON;
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uint32_t _0x184;
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uint32_t _0x188;
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uint32_t _0x18C;
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uint32_t _0x190;
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uint32_t _0x194;
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uint32_t _0x198;
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uint32_t FUSE_DEBUG_AUTH_OVERRIDE;
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uint32_t _0x1A0;
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uint32_t _0x1A4;
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uint32_t _0x1A8;
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uint32_t _0x1AC;
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uint32_t _0x1B0;
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uint32_t _0x1B4;
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uint32_t _0x1B8;
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uint32_t _0x1BC;
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uint32_t _0x1D0;
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uint32_t FUSE_TSENSOR_8;
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uint32_t _0x1D8;
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uint32_t _0x1DC;
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uint32_t _0x1E0;
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uint32_t _0x1E4;
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uint32_t _0x1E8;
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uint32_t _0x1EC;
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uint32_t _0x1F0;
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uint32_t _0x1F4;
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uint32_t _0x1F8;
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uint32_t _0x1FC;
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uint32_t _0x200;
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uint32_t FUSE_RESERVED_CALIB;
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uint32_t _0x208;
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uint32_t _0x20C;
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uint32_t _0x210;
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uint32_t _0x214;
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uint32_t _0x218;
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uint32_t FUSE_TSENSOR_9;
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uint32_t _0x220;
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uint32_t _0x224;
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uint32_t _0x228;
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uint32_t _0x22C;
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uint32_t _0x230;
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uint32_t _0x234;
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uint32_t _0x238;
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uint32_t _0x23C;
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uint32_t _0x240;
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uint32_t _0x244;
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uint32_t _0x248;
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uint32_t _0x24C;
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uint32_t FUSE_USB_CALIB_EXT;
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uint32_t _0x254;
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uint32_t _0x258;
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uint32_t _0x25C;
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uint32_t _0x260;
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uint32_t _0x264;
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uint32_t _0x268;
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uint32_t _0x26C;
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uint32_t _0x270;
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uint32_t _0x274;
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uint32_t _0x278;
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uint32_t _0x27C;
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uint32_t FUSE_SPARE_BIT[0x20];
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} fuse_chip_registers_t;
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#define FUSE_REGS ((volatile fuse_registers_t *)(0x7000F800))
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#define FUSE_CHIP_REGS ((volatile fuse_chip_registers_t *)(0x7000F900))
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#endif
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@ -18,6 +18,7 @@
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#include "lp0.h"
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#include "mc.h"
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#include "pmc.h"
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#include "misc.h"
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#include "timer.h"
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void reboot(void) {
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@ -39,6 +40,9 @@ void lp0_entry_main(warmboot_metadata_t *meta) {
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disable_bpmp_access_to_dram();
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}
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/* Configure debugging depending on FUSE_PRODUCTION_MODE */
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configure_device_dbg_settings();
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/* TODO: stuff */
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while (true) { /* TODO: Halt BPMP */ }
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47
exosphere/lp0fw/src/misc.c
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47
exosphere/lp0fw/src/misc.c
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/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include "utils.h"
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#include "misc.h"
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#include "fuse.h"
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#include "sysreg.h"
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#include "pmc.h"
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void configure_device_dbg_settings(void) {
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/* Enable RTCK daisychaining by setting TBE bit. */
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APB_MISC_PP_CONFIG_CTL_0 = 0x80;
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/* Literally none of this is documented in the TRM, lol. */
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if (FUSE_CHIP_REGS->FUSE_SECURITY_MODE == 1) {
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uint32_t secure_boot_val = 0b0100; /* Sets NIDEN for aarch64. */
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uint32_t misc_val = 0x40;
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if (APBDEV_PMC_STICKY_BITS_0 & 0x40) {
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misc_val = 0x0;
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} else {
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secure_boot_val = 0b1101; /* Sets SPNIDEN, NIDEN, DBGEN for aarch64. */
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}
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SB_PFCFG_0 = (SB_PFCFG_0 & ~0b1111) | secure_boot_val; /* Configures debug bits. */
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APB_MISC_PP_CONFIG_CTL_0 |= misc_val; /* Undocumented, seems to control invasive debugging/JTAG. */
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}
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/* Set sticky bits based SECURITY_MODE. */
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APBDEV_PMC_STICKY_BITS_0 |= FUSE_CHIP_REGS->FUSE_SECURITY_MODE;
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/* Set E_INPUT in PINMUX_AUX_GPIO_PA6_0 */
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PINMUX_AUX_GPIO_PA6_0 |= 0x40;
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}
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33
exosphere/lp0fw/src/misc.h
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33
exosphere/lp0fw/src/misc.h
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/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_WARMBOOT_BIN_MISC_H
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#define EXOSPHERE_WARMBOOT_BIN_MISC_H
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#include <stdint.h>
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#define MISC_BASE (0x70000000)
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#define MAKE_MISC_REG(n) MAKE_REG32(MISC_BASE + n)
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#define APB_MISC_PP_CONFIG_CTL_0 MAKE_MISC_REG(0x024)
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#define PINMUX_AUX_GPIO_PA6_0 MAKE_MISC_REG(0x3244)
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void configure_device_dbg_settings(void);
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#endif
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@ -37,7 +37,7 @@
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#define APBDEV_PMC_SCRATCH13_0 MAKE_PMC_REG(0x084)
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#define APBDEV_PMC_SCRATCH18_0 MAKE_PMC_REG(0x098)
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#define APBDEV_PMC_STICKY_BITS_0 MAKE_PMC_REG(0x2C0)
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#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
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#define APBDEV_PMC_IO_DPD3_REQ_0 MAKE_PMC_REG(0x45C)
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46
exosphere/lp0fw/src/sysreg.h
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46
exosphere/lp0fw/src/sysreg.h
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@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_WARMBOOT_BIN_SYSREG_H
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#define EXOSPHERE_WARMBOOT_BIN_SYSREG_H
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#include <stdint.h>
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#define SYSREG_BASE (0x6000C000)
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n)
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#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n)
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#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004)
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#define SB_CSR_0 MAKE_SB_REG(0x00)
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#define SB_PIROM_START_0 MAKE_SB_REG(0x04)
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#define SB_PFCFG_0 MAKE_SB_REG(0x08)
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#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C)
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#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10)
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#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14)
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#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18)
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#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C)
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#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20)
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#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24)
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#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28)
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#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30)
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#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34)
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#endif
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