mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-18 08:22:04 +00:00
fusee: support mariko in sdmmc
This commit is contained in:
hexkyz
Michael Scire
parent
b14dd4fd5f
commit
6671d46c8d
6 changed files with 189 additions and 68 deletions
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@ -25,6 +25,7 @@
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#include "sdmmc_core.h"
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#if defined(FUSEE_STAGE1_SRC)
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#include "../../../fusee/fusee-primary/src/car.h"
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#include "../../../fusee/fusee-primary/src/fuse.h"
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#include "../../../fusee/fusee-primary/src/pinmux.h"
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#include "../../../fusee/fusee-primary/src/timers.h"
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#include "../../../fusee/fusee-primary/src/apb_misc.h"
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@ -33,6 +34,7 @@
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#include "../../../fusee/fusee-primary/src/max7762x.h"
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#elif defined(FUSEE_STAGE2_SRC)
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#include "../../../fusee/fusee-secondary/src/car.h"
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#include "../../../fusee/fusee-secondary/src/fuse.h"
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#include "../../../fusee/fusee-secondary/src/pinmux.h"
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#include "../../../fusee/fusee-secondary/src/timers.h"
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#include "../../../fusee/fusee-secondary/src/apb_misc.h"
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@ -41,6 +43,7 @@
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#include "../../../fusee/fusee-secondary/src/max7762x.h"
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#elif defined(SEPT_STAGE2_SRC)
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#include "../../../sept/sept-secondary/src/car.h"
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#include "../../../sept/sept-secondary/src/fuse.h"
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#include "../../../sept/sept-secondary/src/pinmux.h"
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#include "../../../sept/sept-secondary/src/timers.h"
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#include "../../../sept/sept-secondary/src/apb_misc.h"
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@ -180,6 +183,11 @@ typedef struct {
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static sdmmc_clk_source_t sdmmc_clk_sources[4] = {0};
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/* Determine the current SoC for Mariko specific code. */
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static bool is_soc_mariko() {
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return (fuse_get_soc_type() == 1);
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}
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/* Check if the SDMMC device clock is held in reset. */
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static bool is_sdmmc_clk_rst(SdmmcControllerNum controller)
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{
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@ -343,6 +351,7 @@ static int sdmmc_get_sdclk_div(SdmmcBusSpeed bus_speed)
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case SDMMC_SPEED_MMC_IDENT:
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return 66;
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case SDMMC_SPEED_SD_IDENT:
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/* return 64; */
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case SDMMC_SPEED_MMC_LEGACY:
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case SDMMC_SPEED_MMC_HS:
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case SDMMC_SPEED_MMC_HS200:
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@ -537,24 +546,27 @@ static void sdmmc_vendor_clock_cntrl_config(sdmmc_t *sdmmc)
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/* Clear the I/O conditioning constants. */
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sdmmc->regs->vendor_clock_cntrl &= ~(SDMMC_CLOCK_TRIM_MASK | SDMMC_CLOCK_TAP_MASK);
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/* Per the TRM, set the PADPIPE clock enable */
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/* Set the PADPIPE clock enable */
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sdmmc->regs->vendor_clock_cntrl |= SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE;
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/* Set the appropriate trim value. */
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switch (sdmmc->controller) {
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case SDMMC_1:
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sdmmc->regs->vendor_clock_cntrl |= SDMMC_CLOCK_TRIM_SDMMC1;
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sdmmc->regs->vendor_clock_cntrl |= (is_soc_mariko() ? SDMMC_CLOCK_TRIM_SDMMC1_MARIKO : SDMMC_CLOCK_TRIM_SDMMC1_ERISTA);
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break;
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case SDMMC_2:
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sdmmc->regs->vendor_clock_cntrl |= SDMMC_CLOCK_TRIM_SDMMC2;
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sdmmc->regs->vendor_clock_cntrl |= (is_soc_mariko() ? SDMMC_CLOCK_TRIM_SDMMC2_MARIKO : SDMMC_CLOCK_TRIM_SDMMC2_ERISTA);
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break;
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case SDMMC_3:
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sdmmc->regs->vendor_clock_cntrl |= SDMMC_CLOCK_TRIM_SDMMC3;
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break;
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case SDMMC_4:
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sdmmc->regs->vendor_clock_cntrl |= SDMMC_CLOCK_TRIM_SDMMC4;
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sdmmc->regs->vendor_clock_cntrl |= (is_soc_mariko() ? SDMMC_CLOCK_TRIM_SDMMC4_MARIKO : SDMMC_CLOCK_TRIM_SDMMC4_ERISTA);
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break;
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}
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/* Clear the SPI_MODE clock enable. */
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sdmmc->regs->vendor_clock_cntrl &= ~(SDMMC_CLOCK_SPI_MODE_CLKEN_OVERRIDE);
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}
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/* Configure automatic calibration. */
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@ -566,11 +578,11 @@ static int sdmmc_autocal_config(sdmmc_t *sdmmc, SdmmcBusVoltage voltage)
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switch (voltage) {
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case SDMMC_VOLTAGE_1V8:
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sdmmc->regs->auto_cal_config &= ~(SDMMC_AUTOCAL_PDPU_CONFIG_MASK);
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sdmmc->regs->auto_cal_config |= SDMMC_AUTOCAL_PDPU_SDMMC1_1V8;
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sdmmc->regs->auto_cal_config |= (is_soc_mariko() ? SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_MARIKO : SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_ERISTA);
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break;
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case SDMMC_VOLTAGE_3V3:
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sdmmc->regs->auto_cal_config &= ~(SDMMC_AUTOCAL_PDPU_CONFIG_MASK);
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sdmmc->regs->auto_cal_config |= SDMMC_AUTOCAL_PDPU_SDMMC1_3V3;
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sdmmc->regs->auto_cal_config |= (is_soc_mariko() ? SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_MARIKO : SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_ERISTA);
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break;
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default:
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sdmmc_error(sdmmc, "uSD does not support requested voltage!");
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@ -624,7 +636,7 @@ static void sdmmc_autocal_run(sdmmc_t *sdmmc, SdmmcBusVoltage voltage)
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sdmmc_get_sd_clock_control(sdmmc);
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/* Delay. */
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udelay(1);
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udelay(2);
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/* Get current time. */
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uint32_t timebase = get_time();
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@ -640,18 +652,51 @@ static void sdmmc_autocal_run(sdmmc_t *sdmmc, SdmmcBusVoltage voltage)
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/* Upon timeout, fall back to standard values. */
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if (sdmmc->controller == SDMMC_1) {
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uint32_t drvup = (voltage == SDMMC_VOLTAGE_3V3) ? 0x12 : 0x11;
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uint32_t drvdn = (voltage == SDMMC_VOLTAGE_3V3) ? 0x12 : 0x15;
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uint32_t drvup, drvdn = 0;
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if (is_soc_mariko()) {
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drvup = 0x8;
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drvdn = 0x8;
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} else {
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drvup = (voltage == SDMMC_VOLTAGE_3V3) ? 0xC : 0xB;
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drvdn = (voltage == SDMMC_VOLTAGE_3V3) ? 0xC : 0xF;
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}
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uint32_t value = padctl->sdmmc1_pad_cfgpadctrl;
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value &= ~(SDMMC1_PAD_CAL_DRVUP_MASK | SDMMC1_PAD_CAL_DRVDN_MASK);
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value |= (drvup << SDMMC1_PAD_CAL_DRVUP_SHIFT);
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value |= (drvdn << SDMMC1_PAD_CAL_DRVDN_SHIFT);
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padctl->sdmmc1_pad_cfgpadctrl = value;
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} else if (sdmmc->controller == SDMMC_2) {
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uint32_t drvup, drvdn = 0;
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if (is_soc_mariko()) {
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drvup = 0xA;
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drvdn = 0xA;
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uint32_t value = padctl->emmc2_pad_cfgpadctrl;
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value &= ~(SDMMC2_PAD_CAL_DRVUP_MASK | SDMMC2_PAD_CAL_DRVDN_MASK);
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value |= (drvup << SDMMC2_PAD_CAL_DRVUP_SHIFT);
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value |= (drvdn << SDMMC2_PAD_CAL_DRVDN_SHIFT);
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padctl->emmc2_pad_cfgpadctrl = value;
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} else {
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drvup = 0x10;
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drvdn = 0x10;
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uint32_t value = padctl->emmc2_pad_cfgpadctrl;
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value &= ~(EMMC2_PAD_DRVUP_COMP_MASK | EMMC2_PAD_DRVDN_COMP_MASK);
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value |= (drvup << EMMC2_PAD_DRVUP_COMP_SHIFT);
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value |= (drvdn << EMMC2_PAD_DRVDN_COMP_SHIFT);
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padctl->emmc2_pad_cfgpadctrl = value;
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}
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} else if (sdmmc->controller == SDMMC_4) {
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uint32_t drvup, drvdn = 0;
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if (is_soc_mariko()) {
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drvup = 0xA;
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drvdn = 0xA;
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} else {
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drvup = 0x10;
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drvdn = 0x10;
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}
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uint32_t value = padctl->emmc4_pad_cfgpadctrl;
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value &= ~(CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK | CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT);
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value &= ~(EMMC4_PAD_DRVUP_COMP_MASK | EMMC4_PAD_DRVDN_COMP_MASK);
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value |= (drvup << EMMC4_PAD_DRVUP_COMP_SHIFT);
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value |= (drvdn << EMMC4_PAD_DRVDN_COMP_SHIFT);
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padctl->emmc4_pad_cfgpadctrl = value;
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}
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@ -794,11 +839,11 @@ static void sdmmc_tap_config(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed)
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switch (sdmmc->controller)
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{
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case SDMMC_1:
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sdmmc->tap_val = 4;
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sdmmc->tap_val = (is_soc_mariko() ? 0xB : 4);
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break;
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case SDMMC_2:
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case SDMMC_4:
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sdmmc->tap_val = 0;
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sdmmc->tap_val = (is_soc_mariko() ? 0xB : 0);
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break;
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case SDMMC_3:
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sdmmc->tap_val = 3;
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@ -982,6 +1027,7 @@ static int sdmmc1_config()
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if (gpio_read(GPIO_MICROSD_CARD_DETECT))
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return 0;
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/* Enable loopback control. */
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padctl->sdmmc1_clk_lpbk_control = 1;
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/* Set up the SDMMC1 pinmux. */
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@ -993,8 +1039,7 @@ static int sdmmc1_config()
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pinmux->sdmmc1_dat0 = PINMUX_DRIVE_2X | PINMUX_PARKED | PINMUX_SELECT_FUNCTION0 | PINMUX_INPUT | PINMUX_PULL_UP;
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/* Ensure the PMC is prepared for the SDMMC1 card to receive power. */
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pmc->no_iopower &= ~PMC_CONTROL_SDMMC1;
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pmc->pwr_det_val |= PMC_CONTROL_SDMMC1;
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pmc->no_iopower &= ~PMC_CONTROL_SDMMC1;
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/* Configure the enable line for the SD card power. */
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pinmux->dmic3_clk = PINMUX_SELECT_FUNCTION1 | PINMUX_PULL_DOWN | PINMUX_INPUT;
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@ -1002,17 +1047,16 @@ static int sdmmc1_config()
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gpio_write(GPIO_MICROSD_SUPPLY_ENABLE, GPIO_LEVEL_HIGH);
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gpio_configure_direction(GPIO_MICROSD_SUPPLY_ENABLE, GPIO_DIRECTION_OUTPUT);
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udelay(1000);
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/* Delay. */
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udelay(10000);
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/* Set up SD card voltages. */
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/* Configure Sdmmc1 IO as 3.3V. */
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pmc->pwr_det_val |= PMC_CONTROL_SDMMC1;
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max77620_regulator_set_voltage(REGULATOR_LDO2, 3300000);
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max77620_regulator_enable(REGULATOR_LDO2, 1);
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udelay(1000);
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padctl->sdmmc1_pad_cfgpadctrl = 0x10000000;
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udelay(1000);
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/* Delay. */
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udelay(130);
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return 1;
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}
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@ -1153,19 +1197,32 @@ int sdmmc_init(sdmmc_t *sdmmc, SdmmcControllerNum controller, SdmmcBusVoltage bu
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/* Update the clock status. */
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sdmmc->is_clk_running = true;
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// Set IO_SPARE[19] (one cycle delay)
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/* Set IO_SPARE[19] (one cycle delay) */
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sdmmc->regs->io_spare |= 0x80000;
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// Clear SEL_VREG
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/* Clear SEL_VREG */
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sdmmc->regs->vendor_io_trim_cntrl &= ~(0x04);
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/* Configure vendor clocking. */
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sdmmc_vendor_clock_cntrl_config(sdmmc);
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/* Set slew codes for SDMMC1 (Erista only). */
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if ((controller == SDMMC_1) && !(is_soc_mariko())) {
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volatile tegra_padctl_t *padctl = padctl_get_regs();
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uint32_t value = padctl->sdmmc1_pad_cfgpadctrl;
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value &= ~(SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK | SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK);
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value |= (0x01 << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT);
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value |= (0x01 << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT);
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padctl->sdmmc1_pad_cfgpadctrl = value;
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}
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// Set SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL to 0x07
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/* Set vref sel. */
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sdmmc->regs->sdmemcomppadctrl &= 0x0F;
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sdmmc->regs->sdmemcomppadctrl |= 0x07;
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if ((controller == SDMMC_1) && is_soc_mariko())
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sdmmc->regs->sdmemcomppadctrl |= 0x00;
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else
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sdmmc->regs->sdmemcomppadctrl |= 0x07;
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/* Configure autocal offsets. */
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if (!sdmmc_autocal_config(sdmmc, bus_voltage)) {
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@ -1635,8 +1692,8 @@ int sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_command_t *cmd, sdmmc_request_t *req, u
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uint32_t cmd_result = 0;
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bool shutdown_sd_clock = false;
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/* Run automatic calibration on each command submission for SDMMC1. */
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if ((sdmmc->controller == SDMMC_1) && !(sdmmc->has_sd))
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/* Run automatic calibration on each command submission for SDMMC1 (Erista only). */
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if ((sdmmc->controller == SDMMC_1) && !(sdmmc->has_sd) && !(is_soc_mariko()))
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sdmmc_autocal_run(sdmmc, sdmmc->bus_voltage);
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/* SD clock is disabled. Enable it. */
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@ -1765,8 +1822,10 @@ int sdmmc_switch_voltage(sdmmc_t *sdmmc)
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/* Reconfigure the regulator. */
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max77620_regulator_set_voltage(REGULATOR_LDO2, 1800000);
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max77620_regulator_enable(REGULATOR_LDO2, 1);
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udelay(150);
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pmc->pwr_det_val &= ~(PMC_CONTROL_SDMMC1);
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/* Reconfigure autocal offsets. */
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if (!sdmmc_autocal_config(sdmmc, SDMMC_VOLTAGE_1V8))
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{
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@ -103,16 +103,22 @@
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#define SDMMC_CLOCK_TAP_SDMMC3 (0x03 << 16)
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#define SDMMC_CLOCK_TAP_SDMMC4 (0x00 << 16)
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#define SDMMC_CLOCK_TRIM_MASK (0xFF << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC1 (0x02 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC2 (0x08 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC1_ERISTA (0x02 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC1_MARIKO (0x0E << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC2_ERISTA (0x08 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC2_MARIKO (0x0D << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC3 (0x03 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC4 (0x08 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC4_ERISTA (0x08 << 24)
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#define SDMMC_CLOCK_TRIM_SDMMC4_MARIKO (0x0D << 24)
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#define SDMMC_CLOCK_SPI_MODE_CLKEN_OVERRIDE (1 << 2)
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#define SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE (1 << 3)
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/* Autocal configuration */
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#define SDMMC_AUTOCAL_PDPU_CONFIG_MASK 0x7F7F
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8 0x7B7B
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3 0x7D00
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_ERISTA 0x7B7B
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_MARIKO 0x0606
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_ERISTA 0x7D00
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#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_MARIKO 0x0000
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#define SDMMC_AUTOCAL_PDPU_SDMMC4_1V8 0x0505
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#define SDMMC_AUTOCAL_START (1 << 31)
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#define SDMMC_AUTOCAL_ENABLE (1 << 29)
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@ -30,13 +30,27 @@
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28)
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#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
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#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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#define EMMC2_PAD_DRVUP_COMP_SHIFT (8)
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#define EMMC2_PAD_DRVDN_COMP_SHIFT (2)
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#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
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#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
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#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
|
||||
|
||||
#define EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
|
||||
|
|
@ -53,22 +67,22 @@
|
|||
|
||||
typedef struct {
|
||||
uint32_t asdbgreg; /* 0x810 */
|
||||
uint32_t reserved0[0x31];
|
||||
uint32_t _0x814[0x31];
|
||||
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
|
||||
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
|
||||
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
|
||||
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
|
||||
uint32_t _todo0[0x6E];
|
||||
uint32_t _0x8E4[0x6E];
|
||||
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
|
||||
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
|
||||
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
|
||||
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
|
||||
uint32_t _todo1[0x03];
|
||||
uint32_t _0xAA8[0x03];
|
||||
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
|
||||
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
|
||||
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
|
||||
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
|
||||
uint32_t _todo2[0x2E];
|
||||
uint32_t _0xAC0[0x2E];
|
||||
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
|
||||
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
|
||||
} tegra_padctl_t;
|
||||
|
|
|
|||
|
|
@ -30,13 +30,27 @@
|
|||
|
||||
#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30)
|
||||
#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
|
||||
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC2_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
|
||||
|
||||
#define EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
|
||||
|
|
@ -53,22 +67,22 @@
|
|||
|
||||
typedef struct {
|
||||
uint32_t asdbgreg; /* 0x810 */
|
||||
uint32_t reserved0[0x31];
|
||||
uint32_t _0x814[0x31];
|
||||
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
|
||||
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
|
||||
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
|
||||
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
|
||||
uint32_t _todo0[0x6E];
|
||||
uint32_t _0x8E4[0x6E];
|
||||
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
|
||||
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
|
||||
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
|
||||
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
|
||||
uint32_t _todo1[0x03];
|
||||
uint32_t _0xAA8[0x03];
|
||||
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
|
||||
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
|
||||
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
|
||||
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
|
||||
uint32_t _todo2[0x2E];
|
||||
uint32_t _0xAC0[0x2E];
|
||||
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
|
||||
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
|
||||
} tegra_padctl_t;
|
||||
|
|
|
|||
|
|
@ -30,13 +30,27 @@
|
|||
|
||||
#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30)
|
||||
#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
|
||||
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC2_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
|
||||
|
||||
#define EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
|
||||
|
|
@ -53,22 +67,22 @@
|
|||
|
||||
typedef struct {
|
||||
uint32_t asdbgreg; /* 0x810 */
|
||||
uint32_t reserved0[0x31];
|
||||
uint32_t _0x814[0x31];
|
||||
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
|
||||
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
|
||||
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
|
||||
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
|
||||
uint32_t _todo0[0x6E];
|
||||
uint32_t _0x8E4[0x6E];
|
||||
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
|
||||
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
|
||||
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
|
||||
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
|
||||
uint32_t _todo1[0x03];
|
||||
uint32_t _0xAA8[0x03];
|
||||
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
|
||||
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
|
||||
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
|
||||
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
|
||||
uint32_t _todo2[0x2E];
|
||||
uint32_t _0xAC0[0x2E];
|
||||
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
|
||||
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
|
||||
} tegra_padctl_t;
|
||||
|
|
|
|||
|
|
@ -30,13 +30,27 @@
|
|||
|
||||
#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30)
|
||||
#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
|
||||
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
|
||||
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC2_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
|
||||
|
||||
#define EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
|
||||
|
|
@ -53,22 +67,22 @@
|
|||
|
||||
typedef struct {
|
||||
uint32_t asdbgreg; /* 0x810 */
|
||||
uint32_t reserved0[0x31];
|
||||
uint32_t _0x814[0x31];
|
||||
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
|
||||
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
|
||||
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
|
||||
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
|
||||
uint32_t _todo0[0x6E];
|
||||
uint32_t _0x8E4[0x6E];
|
||||
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
|
||||
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
|
||||
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
|
||||
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
|
||||
uint32_t _todo1[0x03];
|
||||
uint32_t _0xAA8[0x03];
|
||||
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
|
||||
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
|
||||
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
|
||||
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
|
||||
uint32_t _todo2[0x2E];
|
||||
uint32_t _0xAC0[0x2E];
|
||||
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
|
||||
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
|
||||
} tegra_padctl_t;
|
||||
|
|
|
|||
Loading…
Reference in a new issue