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https://github.com/Atmosphere-NX/Atmosphere.git
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Implement flush_dcache_all_tzram_pa and invalidate_icache_all_inner_shareable_tzram_pa for the crt0s
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parent
e5f293e004
commit
6be5b0a52f
5 changed files with 38 additions and 17 deletions
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@ -15,7 +15,8 @@ void invalidate_dcache_all(void);
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void flush_dcache_range(const void *start, const void *end);
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void invalidate_dcache_range(const void *start, const void *end);
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void invalidate_icache_inner_shareable(void);
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void invalidate_icache_all_inner_shareable(void);
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void invalidate_icache_all(void);
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void finalize_powerdown(void);
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void call_with_stack_pointer(uintptr_t stack_pointer, void (*function)(void));
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@ -217,17 +217,28 @@ invalidate_dcache_range:
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*
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* invalidate all icache entries.
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*/
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.section .text.invalidate_icache_inner_shareable, "ax", %progbits
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.type invalidate_icache_inner_shareable, %function
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.global invalidate_icache_inner_shareable
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invalidate_icache_inner_shareable:
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.section .text.invalidate_icache_all_inner_shareable, "ax", %progbits
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.type invalidate_icache_all_inner_shareable, %function
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.global invalidate_icache_all_inner_shareable
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invalidate_icache_all_inner_shareable:
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dsb ish
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isb
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ic ialluis
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dsb ish
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isb
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ret
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.section .text.invalidate_icache_all, "ax", %progbits
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.type invalidate_icache_all, %function
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.global invalidate_icache_all
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invalidate_icache_all:
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dsb sy
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isb
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ic iallu
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dsb sy
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isb
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ret
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/* Final steps before power down. */
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.section .text.finalize_powerdown, "ax", %progbits
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.type finalize_powerdown, %function
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@ -255,7 +266,7 @@ finalize_powerdown:
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/* Disable receiving instruction cache/tbl maintenance operations. */
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mrs x0, s3_1_c15_c2_1
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and x0, x0, #0xffffffffffffffbf
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msr s3_1_c15_c2_1, x0
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msr s3_1_c15_c2_1, x0
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/* Prepare GICC */
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bl intr_prepare_gicc_for_sleep
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/* Set OS double lock */
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@ -267,11 +278,11 @@ finalize_powerdown:
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wait_for_power_off:
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wfi
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b wait_for_power_off
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/* Call a function with desired stack pointer. */
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.section .text.call_with_stack_pointer, "ax", %progbits
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.type call_with_stack_pointer, %function
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.global call_with_stack_pointer
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call_with_stack_pointer:
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mov sp, x0
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br x1
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br x1
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@ -12,7 +12,7 @@ extern const uint8_t __vectors_start__[], __vectors_end__[], __vectors_lma__[];
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/* warmboot_init.c */
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void set_memory_registers_enable_mmu(void);
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void flush_dcache_all_tzram_pa(void);
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void invalidate_icache_all_tzram_pa(void);
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void invalidate_icache_all_inner_shareable_tzram_pa(void);
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static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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@ -130,7 +130,7 @@ void coldboot_init(void) {
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set_memory_registers_enable_mmu();
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flush_dcache_all_tzram_pa();
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invalidate_icache_all_tzram_pa();
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invalidate_icache_all_inner_shareable_tzram_pa();
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/* At this point we can access all the mapped segments */
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/* TODO: zero-initialize the cpu context */
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/* Nintendo clears the (emtpy) pk2ldr's BSS section here , but we embed it 0-filled in the binary */
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@ -19,7 +19,7 @@ static void setup_se(void) {
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/* Sanity check the Security Engine. */
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se_verify_flags_cleared();
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/* Initialize Interrupts. */
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intr_initialize_gic_nonsecure();
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@ -380,7 +380,7 @@ void load_package2(void) {
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/* Clean up cache. */
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flush_dcache_all();
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invalidate_icache_inner_shareable();
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invalidate_icache_all_inner_shareable();
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/* Set CORE0 entrypoint for Package2. */
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set_core_entrypoint_and_argument(0, DRAM_BASE_PHYSICAL + header.metadata.entrypoint, 0);
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@ -1,16 +1,25 @@
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#include "utils.h"
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#include "memory_map.h"
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#include "arm.h"
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extern const uint8_t __main_start__[];
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/* start.s */
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void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr,
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uint32_t tcr, uint32_t cptr, uint64_t mair, uint32_t sctlr);
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void flush_dcache_all_tzram_pa(void) {
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/* TODO */
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__attribute__((target("cmodel=large"))) void flush_dcache_all_tzram_pa(void) {
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uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
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uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
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uintptr_t v = (uintptr_t)flush_dcache_all - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
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((void (*)(void))v)();
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}
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void invalidate_icache_all_tzram_pa(void) {
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/* TODO */
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__attribute__((target("cmodel=large"))) void invalidate_icache_all_inner_shareable_tzram_pa(void) {
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uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
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uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
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uintptr_t v = (uintptr_t)invalidate_icache_all_inner_shareable - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
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((void (*)(void))v)();
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}
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uintptr_t get_warmboot_crt0_stack_address(void) {
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