mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-22 20:06:40 +00:00
i2c: implement BusAccessor except Send/Receive/WriteHeader
This commit is contained in:
Michael Scire
SciresM
parent
e5bf06254a
commit
6ff58fa4b3
4 changed files with 372 additions and 33 deletions
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@ -27,7 +27,7 @@ namespace ams::regulator {
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void CloseSession(RegulatorSession *session);
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bool GetVoltageEnabled(RegulatorSession *session);
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Result SetVoltageEnabled(RegulatorSession *session);
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Result SetVoltageEnabled(RegulatorSession *session, bool enabled);
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Result SetVoltageValue(RegulatorSession *session, u32 micro_volts);
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@ -64,7 +64,7 @@ namespace ams::i2c::driver::board::nintendo_nx::impl {
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/* Initialize our interrupt event. */
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os::InitializeInterruptEvent(std::addressof(this->interrupt_event), this->interrupt_name, os::EventClearMode_ManualClear);
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os::ClearInterruptEvent(std::addressof(this->interrupt_event);
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os::ClearInterruptEvent(std::addressof(this->interrupt_event));
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/* If we're not power bus, perform power management init. */
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if (!this->is_power_bus) {
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@ -115,7 +115,9 @@ namespace ams::i2c::driver::board::nintendo_nx::impl {
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/* Increment our user count -- if we're not the last user, we're done. */
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AMS_ASSERT(this->user_count > 0);
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--this->user_count;
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R_SUCCEED_IF(this->user_count > 0);
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if (this->user_count > 0) {
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return;
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}
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/* Finalize our interrupt event. */
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os::FinalizeInterruptEvent(std::addressof(this->interrupt_event));
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@ -140,33 +142,129 @@ namespace ams::i2c::driver::board::nintendo_nx::impl {
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}
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Result I2cBusAccessor::Send(I2cDeviceProperty *device, const void *src, size_t src_size, TransactionOption option) {
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/* TODO */
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AMS_ABORT();
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/* Check pre-conditions. */
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AMS_ASSERT(device != nullptr);
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AMS_ASSERT(src != nullptr);
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AMS_ASSERT(src_size > 0);
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if (this->is_power_bus) {
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AMS_ASSERT(this->state == State::Initialized || this->state == State::Suspended);
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} else {
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AMS_ASSERT(this->state == State::Initialized);
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}
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/* Send the data. */
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return this->Send(static_cast<const u8 *>(src), src_size, option, device->GetAddress(), device->GetAddressingMode());
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}
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Result I2cBusAccessor::Receive(void *dst, size_t dst_size, I2cDeviceProperty *device, TransactionOption option) {
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/* TODO */
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AMS_ABORT();
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/* Check pre-conditions. */
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AMS_ASSERT(device != nullptr);
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AMS_ASSERT(dst != nullptr);
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AMS_ASSERT(dst_size > 0);
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if (this->is_power_bus) {
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AMS_ASSERT(this->state == State::Initialized || this->state == State::Suspended);
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} else {
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AMS_ASSERT(this->state == State::Initialized);
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}
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/* Send the data. */
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return this->Receive(static_cast<u8 *>(dst), dst_size, option, device->GetAddress(), device->GetAddressingMode());
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}
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void I2cBusAccessor::SuspendBus() {
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/* TODO */
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AMS_ABORT();
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/* Check that state is valid. */
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AMS_ASSERT(this->state == State::Initialized);
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/* Acquire exclusive access. */
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std::scoped_lock lk(this->user_count_mutex);
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/* If we need to, disable clock/voltage appropriately. */
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if (!this->is_power_bus && this->user_count > 0) {
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/* Disable clock. */
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{
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/* Open a clkrst session. */
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clkrst::ClkRstSession clkrst_session;
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R_ABORT_UNLESS(clkrst::OpenSession(std::addressof(clkrst_session), this->device_code));
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ON_SCOPE_EXIT { clkrst::CloseSession(std::addressof(clkrst_session)); };
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/* Set clock disabled for the session. */
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clkrst::SetClockDisabled(std::addressof(clkrst_session));
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}
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/* Disable voltage. */
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if (this->has_regulator_session) {
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regulator::SetVoltageEnabled(std::addressof(this->regulator_session), false);
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}
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}
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/* Update state. */
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this->state = State::Suspended;
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}
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void I2cBusAccessor::SuspendPowerBus() {
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/* TODO */
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AMS_ABORT();
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/* Check that state is valid. */
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AMS_ASSERT(this->state == State::Suspended);
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/* Acquire exclusive access. */
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std::scoped_lock lk(this->user_count_mutex);
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/* If we need to, disable clock/voltage appropriately. */
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if (this->is_power_bus && this->user_count > 0) {
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/* Nothing should actually be done here. */
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}
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/* Update state. */
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this->state = State::PowerBusSuspended;
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}
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void I2cBusAccessor::ResumeBus() {
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/* TODO */
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AMS_ABORT();
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/* Check that state is valid. */
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AMS_ASSERT(this->state == State::Suspended);
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/* Acquire exclusive access. */
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std::scoped_lock lk(this->user_count_mutex);
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/* If we need to, enable clock/voltage appropriately. */
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if (!this->is_power_bus && this->user_count > 0) {
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/* Enable voltage. */
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if (this->has_regulator_session) {
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/* Check whether voltage was already enabled. */
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const bool was_enabled = regulator::GetVoltageEnabled(std::addressof(this->regulator_session));
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/* NOTE: Nintendo does not check the result of this call. */
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regulator::SetVoltageEnabled(std::addressof(this->regulator_session), true);
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/* If we enabled voltage, delay to give our enable time to take. */
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if (!was_enabled) {
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os::SleepThread(TimeSpan::FromMicroSeconds(560));
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}
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}
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/* Execute initial config, which will enable clock as relevant. */
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this->ExecuteInitialConfig();
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}
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/* Update state. */
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this->state = State::Initialized;
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}
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void I2cBusAccessor::ResumePowerBus() {
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/* TODO */
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AMS_ABORT();
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/* Check that state is valid. */
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AMS_ASSERT(this->state == State::PowerBusSuspended);
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/* Acquire exclusive access. */
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std::scoped_lock lk(this->user_count_mutex);
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/* If we need to, enable clock/voltage appropriately. */
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if (this->is_power_bus && this->user_count > 0) {
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/* Execute initial config, which will enable clock as relevant. */
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this->ExecuteInitialConfig();
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}
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/* Update state. */
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this->state = State::Suspended;
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}
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Result I2cBusAccessor::TryOpenRegulatorSession() {
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@ -188,8 +286,20 @@ namespace ams::i2c::driver::board::nintendo_nx::impl {
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}
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void I2cBusAccessor::ExecuteInitialConfig() {
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/* TODO */
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AMS_ABORT();
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/* Lock exclusive access to registers. */
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std::scoped_lock lk(this->register_mutex);
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/* Reset the controller. */
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this->ResetController();
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/* Set clock registers. */
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this->SetClockRegisters(this->speed_mode);
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/* Set packet mode registers. */
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this->SetPacketModeRegisters();
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/* Flush fifos. */
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this->FlushFifos();
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}
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Result I2cBusAccessor::Send(const u8 *src, size_t src_size, TransactionOption option, u16 slave_address, AddressingMode addressing_mode) {
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@ -208,38 +318,231 @@ namespace ams::i2c::driver::board::nintendo_nx::impl {
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}
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void I2cBusAccessor::ResetController() const {
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/* TODO */
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AMS_ABORT();
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/* Reset the controller. */
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if (!this->is_power_bus) {
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/* Open a clkrst session. */
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clkrst::ClkRstSession clkrst_session;
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R_ABORT_UNLESS(clkrst::OpenSession(std::addressof(clkrst_session), this->device_code));
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ON_SCOPE_EXIT { clkrst::CloseSession(std::addressof(clkrst_session)); };
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/* Reset the controller, setting clock rate to 408 MHz / 5 (to account for clock divisor). */
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/* NOTE: Nintendo does not check result for any of these calls. */
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clkrst::SetResetAsserted(std::addressof(clkrst_session));
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clkrst::SetClockRate(std::addressof(clkrst_session), 408'000'000 / (4 + 1));
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clkrst::SetResetDeasserted(std::addressof(clkrst_session));
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}
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}
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void I2cBusAccessor::ClearBus() const {
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/* TODO */
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AMS_ABORT();
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/* Try to clear the bus up to three times. */
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constexpr int MaxRetryCount = 3;
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constexpr int BusyLoopMicroSeconds = 1000;
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int try_count = 0;
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bool need_retry;
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do {
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/* Update trackers. */
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++try_count;
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need_retry = false;
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/* Reset the controller. */
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this->ResetController();
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/* Configure the sclk threshold for bus clear config. */
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reg::Write(this->registers->bus_clear_config, I2C_REG_BITS_VALUE(BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD, 9));
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/* Set stop cond and terminate in bus clear config. */
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reg::ReadWrite(this->registers->bus_clear_config, I2C_REG_BITS_ENUM(BUS_CLEAR_CONFIG_BC_STOP_COND, STOP));
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reg::ReadWrite(this->registers->bus_clear_config, I2C_REG_BITS_ENUM(BUS_CLEAR_CONFIG_BC_TERMINATE, IMMEDIATE));
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/* Set master config load, busy loop up to 1ms for it to take. */
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reg::ReadWrite(this->registers->config_load, I2C_REG_BITS_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, ENABLE));
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const os::Tick start_tick_a = os::GetSystemTick();
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while (reg::HasValue(this->registers->config_load, I2C_REG_BITS_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, ENABLE))) {
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if ((os::GetSystemTick() - start_tick_a).ToTimeSpan().GetMicroSeconds() > BusyLoopMicroSeconds) {
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need_retry = true;
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break;
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}
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}
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if (need_retry) {
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continue;
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}
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/* Set bus clear enable, wait up to 1ms for it to take. */
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reg::ReadWrite(this->registers->bus_clear_config, I2C_REG_BITS_ENUM(BUS_CLEAR_CONFIG_BC_ENABLE, ENABLE));
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const os::Tick start_tick_b = os::GetSystemTick();
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while (reg::HasValue(this->registers->bus_clear_config, I2C_REG_BITS_ENUM(BUS_CLEAR_CONFIG_BC_ENABLE, ENABLE))) {
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if ((os::GetSystemTick() - start_tick_b).ToTimeSpan().GetMicroSeconds() > BusyLoopMicroSeconds) {
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need_retry = true;
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break;
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}
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}
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if (need_retry) {
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continue;
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}
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/* Wait up to 1ms for the bus clear to complete. */
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const os::Tick start_tick_c = os::GetSystemTick();
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while (reg::HasValue(this->registers->bus_clear_status, I2C_REG_BITS_ENUM(BUS_CLEAR_STATUS_BC_STATUS, NOT_CLEARED))) {
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if ((os::GetSystemTick() - start_tick_c).ToTimeSpan().GetMicroSeconds() > BusyLoopMicroSeconds) {
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need_retry = true;
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break;
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}
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}
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if (need_retry) {
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continue;
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}
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} while (try_count < MaxRetryCount && need_retry);
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}
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void I2cBusAccessor::SetClockRegisters(SpeedMode speed_mode) {
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/* TODO */
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AMS_ABORT();
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/* Determine parameters for the speed mode. */
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u32 t_high, t_low, clk_div, debounce, src_div;
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bool high_speed = false;
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if (this->is_power_bus) {
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t_high = 0x02;
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t_low = 0x04;
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clk_div = 0x05;
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debounce = 0x02;
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} else {
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switch (speed_mode) {
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case SpeedMode_Standard:
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t_high = 0x02;
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t_low = 0x04;
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clk_div = 0x19;
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debounce = 0x02;
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src_div = 0x13;
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break;
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case SpeedMode_Fast:
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t_high = 0x02;
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t_low = 0x04;
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clk_div = 0x19;
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debounce = 0x02;
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src_div = 0x04;
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break;
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case SpeedMode_FastPlus:
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t_high = 0x02;
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t_low = 0x04;
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clk_div = 0x10;
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debounce = 0x00;
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src_div = 0x02;
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break;
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case SpeedMode_HighSpeed:
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t_high = 0x03;
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t_low = 0x08;
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clk_div = 0x02;
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debounce = 0x00;
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src_div = 0x02;
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high_speed = true;
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break;
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AMS_UNREACHABLE_DEFAULT_CASE();
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}
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}
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/* Write the clock divisors. */
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if (high_speed) {
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reg::Write(this->registers->hs_interface_timing_0, I2C_REG_BITS_VALUE(HS_INTERFACE_TIMING_0_HS_THIGH, t_high),
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I2C_REG_BITS_VALUE(HS_INTERFACE_TIMING_0_HS_TLOW, t_low));
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reg::Write(this->registers->clk_divisor_register, I2C_REG_BITS_VALUE(CLK_DIVISOR_REGISTER_HSMODE, clk_div));
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} else {
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reg::Write(this->registers->interface_timing_0, I2C_REG_BITS_VALUE(INTERFACE_TIMING_0_THIGH, t_high),
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I2C_REG_BITS_VALUE(INTERFACE_TIMING_0_TLOW, t_low));
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reg::Write(this->registers->clk_divisor_register, I2C_REG_BITS_VALUE(CLK_DIVISOR_REGISTER_STD_FAST_MODE, clk_div));
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}
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/* Configure debounce. */
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reg::Write(this->registers->cnfg, I2C_REG_BITS_VALUE(I2C_CNFG_DEBOUNCE_CNT, debounce));
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reg::Read(this->registers->cnfg);
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/* Set the clock rate, if we should. */
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if (!this->is_power_bus) {
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/* Open a clkrst session. */
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clkrst::ClkRstSession clkrst_session;
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R_ABORT_UNLESS(clkrst::OpenSession(std::addressof(clkrst_session), this->device_code));
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ON_SCOPE_EXIT { clkrst::CloseSession(std::addressof(clkrst_session)); };
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/* Reset the controller, setting clock rate to 408 MHz / (src_div + 1). */
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/* NOTE: Nintendo does not check result for any of these calls. */
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clkrst::SetResetAsserted(std::addressof(clkrst_session));
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clkrst::SetClockRate(std::addressof(clkrst_session), 408'000'000 / (src_div + 1));
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clkrst::SetResetDeasserted(std::addressof(clkrst_session));
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}
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}
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void I2cBusAccessor::SetPacketModeRegisters() {
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/* TODO */
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AMS_ABORT();
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/* Set packet mode enable. */
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reg::ReadWrite(this->registers->cnfg, I2C_REG_BITS_ENUM(I2C_CNFG_PACKET_MODE_EN, GO));
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/* Set master config load. */
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reg::ReadWrite(this->registers->config_load, I2C_REG_BITS_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, ENABLE));
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/* Set tx/fifo triggers to default (maximum values). */
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reg::Write(this->registers->fifo_control, I2C_REG_BITS_VALUE(FIFO_CONTROL_RX_FIFO_TRIG, 7),
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I2C_REG_BITS_VALUE(FIFO_CONTROL_TX_FIFO_TRIG, 7));
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}
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Result I2cBusAccessor::FlushFifos() {
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/* TODO */
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AMS_ABORT();
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/* Flush the fifo. */
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reg::Write(this->registers->fifo_control, I2C_REG_BITS_VALUE(FIFO_CONTROL_RX_FIFO_TRIG, 7),
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I2C_REG_BITS_VALUE(FIFO_CONTROL_TX_FIFO_TRIG, 7),
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I2C_REG_BITS_ENUM (FIFO_CONTROL_RX_FIFO_FLUSH, SET),
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I2C_REG_BITS_ENUM (FIFO_CONTROL_TX_FIFO_FLUSH, SET));
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/* Wait up to 5 ms for the flush to complete. */
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int count = 0;
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while (!reg::HasValue(this->registers->fifo_control, I2C_REG_BITS_ENUM(FIFO_CONTROL_FIFO_FLUSH, RX_UNSET_TX_UNSET))) {
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R_UNLESS((++count < 5), i2c::ResultBusBusy());
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os::SleepThread(TimeSpan::FromMilliSeconds(1));
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}
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return ResultSuccess();
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}
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Result I2cBusAccessor::GetTransactionResult() const {
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/* TODO */
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AMS_ABORT();
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/* Get packet status/interrupt status. */
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volatile u32 packet_status = reg::Read(this->registers->packet_transfer_status);
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volatile u32 interrupt_status = reg::Read(this->registers->interrupt_status_register);
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/* Check for ack. */
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R_UNLESS(reg::HasValue(packet_status, I2C_REG_BITS_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_DATA, UNSET)), i2c::ResultNoAck());
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R_UNLESS(reg::HasValue(packet_status, I2C_REG_BITS_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR, UNSET)), i2c::ResultNoAck());
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R_UNLESS(reg::HasValue(interrupt_status, I2C_REG_BITS_ENUM(INTERRUPT_STATUS_REGISTER_NOACK, UNSET)), i2c::ResultNoAck());
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/* If we lost arbitration, we'll need to clear the bus. */
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auto clear_guard = SCOPE_GUARD { this->ClearBus(); };
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/* Check for arb lost. */
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R_UNLESS(reg::HasValue(packet_status, I2C_REG_BITS_ENUM(PACKET_TRANSFER_STATUS_ARB_LOST, UNSET)), i2c::ResultBusBusy());
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R_UNLESS(reg::HasValue(interrupt_status, I2C_REG_BITS_ENUM(INTERRUPT_STATUS_REGISTER_ARB_LOST, UNSET)), i2c::ResultBusBusy());
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clear_guard.Cancel();
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return ResultSuccess();
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}
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void I2cBusAccessor::HandleTransactionError(Result result) {
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/* TODO */
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AMS_ABORT();
|
||||
R_TRY_CATCH(result) {
|
||||
R_CATCH(i2c::ResultNoAck, i2c::ResultBusBusy) {
|
||||
/* Reset the controller. */
|
||||
this->ResetController();
|
||||
|
||||
/* Set clock registers. */
|
||||
this->SetClockRegisters(this->speed_mode);
|
||||
|
||||
/* Set packet mode registers. */
|
||||
this->SetPacketModeRegisters();
|
||||
|
||||
/* Flush fifos. */
|
||||
this->FlushFifos();
|
||||
}
|
||||
} R_END_TRY_CATCH_WITH_ABORT_UNLESS;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,11 +25,17 @@
|
|||
#define I2C_I2C_CMD_ADDR0 (0x004)
|
||||
#define I2C_I2C_CMD_DATA1 (0x00C)
|
||||
#define I2C_I2C_STATUS (0x01C)
|
||||
#define I2C_PACKET_TRANSFER_STATUS (0x058)
|
||||
#define I2C_FIFO_CONTROL (0x05C)
|
||||
#define I2C_INTERRUPT_STATUS_REGISTER (0x068)
|
||||
#define I2C_CLK_DIVISOR_REGISTER (0x06C)
|
||||
#define I2C_BUS_CLEAR_CONFIG (0x084)
|
||||
#define I2C_BUS_CLEAR_STATUS (0x088)
|
||||
#define I2C_CONFIG_LOAD (0x08C)
|
||||
#define I2C_INTERFACE_TIMING_0 (0x094)
|
||||
#define I2C_INTERFACE_TIMING_1 (0x098)
|
||||
#define I2C_HS_INTERFACE_TIMING_0 (0x094)
|
||||
#define I2C_HS_INTERFACE_TIMING_1 (0x098)
|
||||
|
||||
#define I2C_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (I2C, NAME)
|
||||
#define I2C_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (I2C, NAME, VALUE)
|
||||
|
|
@ -46,6 +52,7 @@
|
|||
DEFINE_I2C_REG(I2C_CNFG_LENGTH, 1, 3);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_CMD1, 6, WRITE, READ);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_SEND, 9, NOP, GO);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_PACKET_MODE_EN, 9, NOP, GO);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_NEW_MASTER_FSM, 11, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_THREE_BIT_ENUM(I2C_CNFG_DEBOUNCE_CNT, 12, NO_DEBOUNCE, DEBOUNCE_2T, DEBOUNCE_4T, DEBOUNCE_6T, DEBOUNCE_8T, DEBOUNCE_10T, DEBOUNCE_12T, DEBOUNCE_14T);
|
||||
|
||||
|
|
@ -58,7 +65,24 @@ DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD1_STAT, 0, SL1_XFER_SUCCESSFUL, SL1_N
|
|||
DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD2_STAT, 4, SL2_XFER_SUCCESSFUL, SL2_NOACK_FOR_BYTE1, SL2_NOACK_FOR_BYTE2, SL2_NOACK_FOR_BYTE3, SL2_NOACK_FOR_BYTE4, SL2_NOACK_FOR_BYTE5, SL2_NOACK_FOR_BYTE6, SL2_NOACK_FOR_BYTE7, SL2_NOACK_FOR_BYTE8, SL2_NOACK_FOR_BYTE9, SL2_NOACK_FOR_BYTE10, RESERVED11, RESERVED12, RESERVED13, RESERVED14, RESERVED15);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_STATUS_BUSY, 8, NOT_BUSY, BUSY);
|
||||
|
||||
/* PACKET_TRANSFER_STATUS */
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_CONTROLLER_BUSY, 0, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_ARB_LOST, 1, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_DATA, 2, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR, 3, UNSET, SET);
|
||||
|
||||
/* FIFO_CONTROL */
|
||||
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_RX_FIFO_FLUSH, 0, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_TX_FIFO_FLUSH, 1, UNSET, SET);
|
||||
|
||||
DEFINE_I2C_REG_TWO_BIT_ENUM(FIFO_CONTROL_FIFO_FLUSH, 0, RX_UNSET_TX_UNSET, RX_SET_TX_UNSET, RX_UNSET_TX_SET, RX_SET_TX_SET);
|
||||
|
||||
DEFINE_I2C_REG(FIFO_CONTROL_RX_FIFO_TRIG, 2, 3);
|
||||
DEFINE_I2C_REG(FIFO_CONTROL_TX_FIFO_TRIG, 5, 3);
|
||||
|
||||
/* INTERRUPT_STATUS_REGISTER */
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_ARB_LOST, 2, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_NOACK, 3, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_BUS_CLEAR_DONE, 11, UNSET, SET);
|
||||
|
||||
/* CLK_DIVISOR_REGISTER */
|
||||
|
|
@ -71,8 +95,20 @@ DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_TERMINATE, 1, THRESHOLD, IMMEDIATE);
|
|||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_STOP_COND, 2, NO_STOP, STOP);
|
||||
DEFINE_I2C_REG(BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD, 16, 8);
|
||||
|
||||
/* BUS_CLEAR_STATUS */
|
||||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_STATUS_BC_STATUS, 0, NOT_CLEARED, CLEARED);
|
||||
|
||||
/* CONFIG_LOAD */
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, 0, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_SLV_CONFIG_LOAD, 1, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_TIMEOUT_CONFIG_LOAD, 2, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG(CONFIG_LOAD_RESERVED_BIT_5, 5, 1);
|
||||
|
||||
/* INTERFACE_TIMING_0 */
|
||||
DEFINE_I2C_REG(INTERFACE_TIMING_0_TLOW, 0, 6);
|
||||
DEFINE_I2C_REG(INTERFACE_TIMING_0_THIGH, 8, 6);
|
||||
|
||||
/* HS_INTERFACE_TIMING_0 */
|
||||
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_TLOW, 0, 6);
|
||||
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_THIGH, 8, 6);
|
||||
|
||||
|
|
|
|||
|
|
@ -39,8 +39,8 @@ namespace ams::regulator {
|
|||
return true;
|
||||
}
|
||||
|
||||
Result SetVoltageEnabled(RegulatorSession *session) {
|
||||
AMS_UNUSED(session);
|
||||
Result SetVoltageEnabled(RegulatorSession *session, bool enabled) {
|
||||
AMS_UNUSED(session, enabled);
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue