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warmboot: add crail power on code
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parent
754aaecc18
commit
72594c6783
3 changed files with 46 additions and 3 deletions
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@ -63,6 +63,9 @@
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 MAKE_CAR_REG(0x440)
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 MAKE_CAR_REG(0x440)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 MAKE_CAR_REG(0x448)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 MAKE_CAR_REG(0x448)
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0 MAKE_CAR_REG(0x32C)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0 MAKE_CAR_REG(0x44C)
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#define NUM_CAR_BANKS 7
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#define NUM_CAR_BANKS 7
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typedef enum {
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typedef enum {
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@ -25,6 +25,20 @@
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#include "i2c.h"
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#include "i2c.h"
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#include "sysreg.h"
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#include "sysreg.h"
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static void cluster_pmc_enable_partition(uint32_t mask, uint32_t toggle) {
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/* Set toggle if unset. */
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if (!(APBDEV_PMC_PWRGATE_STATUS_0 & mask)) {
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APBDEV_PMC_PWRGATE_TOGGLE_0 = toggle;
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}
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/* Wait until toggle set. */
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while (!(APBDEV_PMC_PWRGATE_STATUS_0 & mask)) { }
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/* Remove clamping. */
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APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = mask;
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while (!(APBDEV_PMC_CLAMP_STATUS_0 & mask)) { }
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}
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void cluster_initialize_cpu(void) {
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void cluster_initialize_cpu(void) {
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/* Hold CoreSight in reset. */
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/* Hold CoreSight in reset. */
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CLK_RST_CONTROLLER_RST_DEV_U_SET_0 = 0x200;
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CLK_RST_CONTROLLER_RST_DEV_U_SET_0 = 0x200;
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@ -88,8 +102,32 @@ void cluster_initialize_cpu(void) {
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CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0 = 0x4;
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CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0 = 0x4;
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CLK_RST_CONTROLLER_RST_DEV_H_CLR_0 = 0x8000;
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CLK_RST_CONTROLLER_RST_DEV_H_CLR_0 = 0x8000;
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/* Enable the PMIC. */
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/* Enable the PMIC, wait 2ms. */
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i2c_enable_pmic();
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i2c_enable_pmic();
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timer_wait(2000);
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/* Enable power to the CRAIL partition. */
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cluster_pmc_enable_partition(1, 0x100);
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/* Remove SW clamp to CRAIL. */
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APBDEV_PMC_SET_SW_CLAMP_0 = 0;
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APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = 1;
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while (!(APBDEV_PMC_CLAMP_STATUS_0 & 1)) { }
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/* Nintendo manually counts down from 8. I am not sure why this happens. */
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{
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volatile int32_t counter = 8;
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while (counter >= 0) {
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counter--;
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}
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}
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/* Power off I2C5. */
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CLK_RST_CONTROLLER_RST_DEV_H_SET_0 = 0x8000;
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CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0 = 0x8000;
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/* Disable clock to CL_DVFS */
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CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0 = 0x08000000;
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/* TODO: This function is enormous */
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/* TODO: This function is enormous */
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}
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}
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@ -31,12 +31,14 @@
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#define APBDEV_PMC_CLAMP_STATUS_0 MAKE_PMC_REG(0x02C)
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#define APBDEV_PMC_CLAMP_STATUS_0 MAKE_PMC_REG(0x02C)
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#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x038)
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#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x030)
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#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0 MAKE_PMC_REG(0x034)
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#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x038)
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#define APBDEV_PMC_SCRATCH12_0 MAKE_PMC_REG(0x080)
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#define APBDEV_PMC_SCRATCH12_0 MAKE_PMC_REG(0x080)
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#define APBDEV_PMC_SCRATCH13_0 MAKE_PMC_REG(0x084)
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#define APBDEV_PMC_SCRATCH13_0 MAKE_PMC_REG(0x084)
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#define APBDEV_PMC_SCRATCH18_0 MAKE_PMC_REG(0x098)
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#define APBDEV_PMC_SCRATCH18_0 MAKE_PMC_REG(0x098)
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#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
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#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
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#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
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#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
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