From 0534e36cf88716c113233f0cfe876e82f6654964 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tomasz=20Mo=C5=84?= Date: Sun, 27 May 2018 17:43:25 +0200 Subject: [PATCH] Set SDMMC controller to SDR104 as a workaround According to Tegra X1 Series Processors Silicon Errata there is possible misalignment of received data which results in a CRC error. The issue is present only in SDR50 mode. --- fusee/fusee-primary/src/sdmmc.c | 3 ++- fusee/fusee-secondary/src/sdmmc.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/fusee/fusee-primary/src/sdmmc.c b/fusee/fusee-primary/src/sdmmc.c index 18f611309..40abccba4 100644 --- a/fusee/fusee-primary/src/sdmmc.c +++ b/fusee/fusee-primary/src/sdmmc.c @@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed, case SDMMC_SPEED_SDR50: mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED; mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH); - sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50); + // Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround. + sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104); execute_tuning = true; tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50; diff --git a/fusee/fusee-secondary/src/sdmmc.c b/fusee/fusee-secondary/src/sdmmc.c index 18f611309..40abccba4 100644 --- a/fusee/fusee-secondary/src/sdmmc.c +++ b/fusee/fusee-secondary/src/sdmmc.c @@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed, case SDMMC_SPEED_SDR50: mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED; mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH); - sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50); + // Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround. + sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104); execute_tuning = true; tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;