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exo: add mariko spare reg write during setup

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This commit is contained in:
Michael Scire 2020-06-29 05:40:09 -07:00
parent 1084817d84
commit 828b170aac
2 changed files with 13 additions and 0 deletions
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7
exosphere/program/source/secmon_setup_warm.cpp
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@ -264,6 +264,13 @@ namespace ams::secmon {
{ {
reg::Write(AHB_ARBC(AHB_GIZMO_TZRAM), (1u << 7)); reg::Write(AHB_ARBC(AHB_GIZMO_TZRAM), (1u << 7));
} }
/* NOTE: This is Mariko only in Nintendo's firmware. */
/* Still, it seems to have no adverse effects on Erista... */
/* TODO: Find a way to get access to SocType this early (fuse driver isn't alive yet), only write on mariko? */
{
reg::ReadWrite(AHB_ARBC(AHB_AHB_SPARE_REG), AHB_REG_BITS_VALUE(AHB_SPARE_REG_AHB_SPARE_REG, 0xE0000));
}
} }
void SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmboot() { void SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmboot() {

6
libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
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@ -23,6 +23,7 @@
#define AHB_MASTER_SWID (0x018) #define AHB_MASTER_SWID (0x018)
#define AHB_MASTER_SWID_1 (0x038) #define AHB_MASTER_SWID_1 (0x038)
#define AHB_GIZMO_TZRAM (0x054) #define AHB_GIZMO_TZRAM (0x054)
#define AHB_AHB_SPARE_REG (0x110)
#define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME) #define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME)
#define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE) #define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE)
@ -39,3 +40,8 @@ DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE);
DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA, 5, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA, 5, ENABLE, DISABLE);
DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB, 6, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB, 6, ENABLE, DISABLE);
DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2, 18, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2, 18, ENABLE, DISABLE);
DEFINE_AHB_REG(AHB_SPARE_REG_CSITE_PADMACRO3_TRIM_SEL, 0, 5);
DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_OBS_OVERRIDE_EN, 5, DISABLE, ENABLE);
DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_APB2JTAG_OVERRIDE_EN, 6, DISABLE, ENABLE);
DEFINE_AHB_REG(AHB_SPARE_REG_AHB_SPARE_REG, 12, 32-12);