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fusee/sept: build fixes

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This commit is contained in:
Michael Scire 2020-12-31 17:37:57 -08:00 committed by SciresM
parent f4e763ce40
commit 96f3c0c387
7 changed files with 145 additions and 128 deletions
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88
fusee/fusee-secondary/src/cluster.c
View file

@ -14,9 +14,9 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdint.h>
#include "cluster.h"
#include "flow.h"
#include "sysreg.h"
@ -37,40 +37,46 @@ static bool is_soc_mariko() {
static void cluster_enable_power(uint32_t regulator) {
switch (regulator) {
case 0: /* Regulator_Max77621 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val &= 0xDF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val = 0x09;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
val = 0x20;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
val = 0x8D;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val &= 0xDF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val = 0x09;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
val = 0x20;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
val = 0x8D;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
}
break;
case 1: /* Regulator_Max77812PhaseConfiguration31 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break;
case 2: /* Regulator_Max77812PhaseConfiguration211 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break;
default: return;
}
@ -78,7 +84,7 @@ static void cluster_enable_power(uint32_t regulator) {
static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
volatile tegra_pmc_t *pmc = pmc_get_regs();
/* Check if the partition has already been turned on. */
if (pmc->pwrgate_status & part) {
return;
@ -110,13 +116,13 @@ static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
void cluster_boot_cpu0(uint32_t entry) {
volatile tegra_car_t *car = car_get_regs();
bool is_mariko = is_soc_mariko();
/* Set ACTIVE_CLUSER to FAST. */
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
/* Enable VddCpu. */
cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
if (!(car->pllx_base & 0x40000000)) {
car->pllx_misc3 &= 0xFFFFFFF7;
udelay(2);
@ -127,7 +133,7 @@ void cluster_boot_cpu0(uint32_t entry) {
car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
car->pllx_base = 0x40404E02;
}
while (!(car->pllx_base & 0x8000000)) {
/* Wait. */
}
@ -139,7 +145,7 @@ void cluster_boot_cpu0(uint32_t entry) {
car->cclk_brst_pol = 0x20008888;
car->super_cclk_div = 0x80000000;
car->clk_enb_v_set = 1;
/* Reboot CORESIGHT. */
clkrst_reboot(CARDEVICE_CORESIGHT);
@ -148,10 +154,10 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Enable CPU rail. */
cluster_pmc_enable_partition(1, 0);
/* Enable cluster 0 non-CPU. */
cluster_pmc_enable_partition(0x8000, 15);
/* Enable CE0. */
cluster_pmc_enable_partition(0x4000, 14);
@ -166,7 +172,7 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Set reset vector. */
SB_AA64_RESET_LOW_0 = (entry | 1);
SB_AA64_RESET_HIGH_0 = 0;
/* Non-secure reset vector write disable. */
SB_CSR_0 = 2;
(void)SB_CSR_0;
@ -174,15 +180,15 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
/* NOTE: This breaks Exosphère. */
/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
/* Clear MSELECT reset. */
rst_disable(CARDEVICE_MSELECT);
if (!is_mariko) {
/* Clear NONCPU reset. */
car->rst_cpug_cmplx_clr = 0x20000000;
}
/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
car->rst_cpug_cmplx_clr = 0x41010001;
}

2
fusee/fusee-secondary/src/fuse.h
View file

@ -470,7 +470,7 @@ uint64_t fuse_get_device_id(void);
uint32_t fuse_get_dram_id(void);
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
uint32_t fuse_get_hardware_type(void);
uint32_t fuse_get_retail_type(void);
uint32_t fuse_get_hardware_state(void);
void fuse_get_hardware_info(void *dst);
bool fuse_is_new_format(void);
uint32_t fuse_get_device_unique_key_generation(void);

4
fusee/fusee-secondary/src/key_derivation.c
View file

@ -15,7 +15,7 @@
*/
#include <stdio.h>
#include "lib/log.h"
#include "../../../fusee/common/log.h"
#include "key_derivation.h"
#include "masterkey.h"
#include "se.h"
@ -229,7 +229,7 @@ int derive_nx_keydata_mariko(uint32_t target_firmware) {
decrypt_data_into_keyslot(0xA, 0xE, devicekey_4x_seed, 0x10);
decrypt_data_into_keyslot(0x7, 0xC, &master_kek_seeds_mariko[target_firmware - MASTERKEY_REVISION_600_610], 0x10);
decrypt_data_into_keyslot(0x7, 0x7, masterkey_seed, 0x10);
/* Setup master key revision, derive older master keys for use. */
return mkey_detect_revision(fuse_get_hardware_state() != 0);
}

23
fusee/fusee-secondary/src/nxboot.c
View file

@ -691,7 +691,7 @@ uint32_t nxboot_main(void) {
FILE *boot0, *pk2file;
void *exosphere_memaddr;
exo_emummc_config_t exo_emummc_cfg;
/* Configure emummc or mount the real NAND. */
if (!nxboot_configure_emummc(&exo_emummc_cfg)) {
emummc = NULL;
@ -771,9 +771,11 @@ uint32_t nxboot_main(void) {
fatal_error("[NXBOOT] Failed to open boot0: %s!\n", strerror(errno));
}
if (is_mariko) {
/* TODO*/
if (package1_read_and_parse_boot0_mariko(&package1loader, &package1loader_size, boot0) == -1) {
fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
}
} else {
if (package1_read_and_parse_boot0(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
}
}
@ -782,12 +784,15 @@ uint32_t nxboot_main(void) {
/* Find the system's target firmware. */
uint32_t target_firmware = nxboot_get_target_firmware(package1loader);
if (!target_firmware)
if (!target_firmware) {
fatal_error("[NXBOOT] Failed to detect target firmware!\n");
else
} else {
print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Detected target firmware %ld!\n", target_firmware);
}
/* Handle TSEC and Sept (Erista only). */
uint8_t tsec_key[0x10] = {0};
uint8_t tsec_root_keys[0x20][0x10] = {0};
if (!is_mariko) {
/* Read the TSEC firmware from a file, otherwise from PK1L. */
if (loader_ctx->tsecfw_path[0] != '\0') {
@ -859,8 +864,6 @@ uint32_t nxboot_main(void) {
print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n");
/* Get the TSEC keys. */
uint8_t tsec_key[0x10] = {0};
uint8_t tsec_root_keys[0x20][0x10] = {0};
if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
/* Detect whether we need to run sept-secondary in order to derive keys. */
if (!get_and_clear_has_run_sept()) {
@ -958,6 +961,8 @@ uint32_t nxboot_main(void) {
} else {
if (is_mariko) {
/* TODO */
warmboot_fw = NULL;
warmboot_fw_size = 0;
} else {
/* Use Atmosphere's warmboot firmware implementation. */
warmboot_fw_size = warmboot_bin_size;
@ -1000,7 +1005,7 @@ uint32_t nxboot_main(void) {
pmc->scratch1 = (uint32_t)warmboot_memaddr;
}
}
/* Handle warmboot security check. */
if (is_mariko) {
/* TODO */
@ -1125,7 +1130,7 @@ uint32_t nxboot_main(void) {
rst_enable(CARDEVICE_AHBDMA);
rst_enable(CARDEVICE_APBDMA);
}
/* Return the memory address for booting CPU0. */
return (uint32_t)exosphere_memaddr;
}

66
sept/sept-primary/src/main.c
View file

@ -38,7 +38,7 @@ static void setup_exception_vectors(void) {
static void mbist_workaround(void)
{
volatile tegra_car_t *car = car_get_regs();
car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
car->plld_base |= 0x40800000u;
car->rst_dev_y_clr = 0x40;
@ -57,7 +57,7 @@ static void mbist_workaround(void)
MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
MAKE_I2S_REG(0x4A0) |= 0x400;
MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
udelay(3);
@ -66,7 +66,7 @@ static void mbist_workaround(void)
car->rst_dev_y_set = 0x40;
car->rst_dev_l_set = 0x18000000;
car->rst_dev_x_set = 0x40000;
/* Clock out enables. */
car->clk_out_enb_h = 0xC0;
car->clk_out_enb_l = 0x80000130;
@ -75,14 +75,14 @@ static void mbist_workaround(void)
car->clk_out_enb_w = 0x402000FC;
car->clk_out_enb_x = 0x23000780;
car->clk_out_enb_y = 0x300;
/* LVL2 clock gate overrides. */
car->lvl2_clk_gate_ovra = 0;
car->lvl2_clk_gate_ovrb = 0;
car->lvl2_clk_gate_ovrc = 0;
car->lvl2_clk_gate_ovrd = 0;
car->lvl2_clk_gate_ovre = 0;
/* Configure clock sources. */
car->plld_base &= 0x1F7FFFFF;
car->clk_source_sor1 &= 0xFFFF3FFF;
@ -93,7 +93,7 @@ static void mbist_workaround(void)
static int tsec_dma_wait_idle()
{
volatile tegra_tsec_t *tsec = tsec_get_regs();
volatile tegra_tsec_t *tsec = tsec_get_regs();
uint32_t timeout = (get_time_ms() + 10000);
while (!(tsec->TSEC_FALCON_DMATRFCMD & 2))
@ -101,13 +101,13 @@ static int tsec_dma_wait_idle()
if (get_time_ms() > timeout)
return 0;
}
return 1;
}
static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset)
{
volatile tegra_tsec_t *tsec = tsec_get_regs();
volatile tegra_tsec_t *tsec = tsec_get_regs();
uint32_t cmd = 0;
if (!is_imem)
@ -123,16 +123,16 @@ static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t ph
}
static int tsec_kfuse_wait_ready()
{
{
uint32_t timeout = (get_time_ms() + 10000);
/* Wait for STATE_DONE. */
while (!(KFUSE_STATE & 0x10000))
{
if (get_time_ms() > timeout)
return 0;
}
/* Check for STATE_CRCPASS. */
if (!(KFUSE_STATE & 0x20000))
return 0;
@ -143,7 +143,7 @@ static int tsec_kfuse_wait_ready()
int load_tsec_fw(void) {
volatile uint32_t* tsec_fw = (volatile uint32_t*)0x40010F00;
const uint32_t tsec_fw_length = MAKE_REG32(0x40010EFC);
volatile tegra_tsec_t *tsec = tsec_get_regs();
/* Enable clocks. */
@ -153,7 +153,7 @@ int load_tsec_fw(void) {
clkrst_reboot(CARDEVICE_SOR0);
clkrst_reboot(CARDEVICE_SOR1);
clkrst_reboot(CARDEVICE_KFUSE);
/* Make sure KFUSE is ready. */
if (!tsec_kfuse_wait_ready())
{
@ -164,16 +164,16 @@ int load_tsec_fw(void) {
clkrst_disable(CARDEVICE_SOR_SAFE);
clkrst_disable(CARDEVICE_TSEC);
clkrst_disable(CARDEVICE_HOST1X);
return -1;
}
/* Configure Falcon. */
tsec->TSEC_FALCON_DMACTL = 0;
tsec->TSEC_FALCON_IRQMSET = 0xFFF2;
tsec->TSEC_FALCON_IRQDEST = 0xFFF0;
tsec->TSEC_FALCON_ITFEN = 3;
/* Make sure the DMA block is idle. */
if (!tsec_dma_wait_idle())
{
@ -184,10 +184,10 @@ int load_tsec_fw(void) {
clkrst_disable(CARDEVICE_SOR_SAFE);
clkrst_disable(CARDEVICE_TSEC);
clkrst_disable(CARDEVICE_HOST1X);
return -2;
}
/* Load firmware. */
tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8;
for (uint32_t addr = 0; addr < tsec_fw_length; addr += 0x100)
@ -201,57 +201,57 @@ int load_tsec_fw(void) {
clkrst_disable(CARDEVICE_SOR_SAFE);
clkrst_disable(CARDEVICE_TSEC);
clkrst_disable(CARDEVICE_HOST1X);
return -3;
}
}
/* Write magic value to HOST1X scratch register. */
MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA;
/* Execute firmware. */
tsec->TSEC_FALCON_MAILBOX1 = 0;
tsec->TSEC_FALCON_MAILBOX0 = 1;
tsec->TSEC_FALCON_BOOTVEC = 0;
tsec->TSEC_FALCON_CPUCTL = 2;
while (true) {
/* Yield to Nintendo's TSEC firmware. */
}
}
int main(void) {
int main(void) {
/* Setup vectors */
setup_exception_vectors();
volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_car_t *car = car_get_regs();
/* Clear the boot reason to avoid problems later */
pmc->scratch200 = 0;
pmc->reset_status = 0;
pmc->rst_status = 0;
//AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
//pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
/* Apply the memory built-in self test workaround. */
mbist_workaround();
/* Reboot SE. */
clkrst_reboot(CARDEVICE_SE);
/* Initialize the fuse driver. */
fuse_init();
/* Don't bother checking SKU, fuses, or bootloader version. */
mc_enable_for_tsec();
/* 7.0.0 package1ldr holds I2C5 in reset, clears SYS clock. */
car->clk_source_sys = 0;
rst_enable(CARDEVICE_I2C5);
load_tsec_fw();
while (true) { }
return 0;
}

2
sept/sept-secondary/linker.ld
View file

@ -13,7 +13,7 @@ PHDRS
MEMORY
{
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
main : ORIGIN = 0x40010000, LENGTH = 0x20000
main : ORIGIN = 0x40010000, LENGTH = 0x28000
low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
}

88
sept/sept-secondary/src/cluster.c
View file

@ -14,9 +14,9 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdint.h>
#include "cluster.h"
#include "flow.h"
#include "sysreg.h"
@ -37,40 +37,46 @@ static bool is_soc_mariko() {
static void cluster_enable_power(uint32_t regulator) {
switch (regulator) {
case 0: /* Regulator_Max77621 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val &= 0xDF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val = 0x09;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
val = 0x20;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
val = 0x8D;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val &= 0xDF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val = 0x09;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
val = 0x20;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
val = 0x8D;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
}
break;
case 1: /* Regulator_Max77812PhaseConfiguration31 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break;
case 2: /* Regulator_Max77812PhaseConfiguration211 */
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
break;
default: return;
}
@ -78,7 +84,7 @@ static void cluster_enable_power(uint32_t regulator) {
static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
volatile tegra_pmc_t *pmc = pmc_get_regs();
/* Check if the partition has already been turned on. */
if (pmc->pwrgate_status & part) {
return;
@ -110,13 +116,13 @@ static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
void cluster_boot_cpu0(uint32_t entry) {
volatile tegra_car_t *car = car_get_regs();
bool is_mariko = is_soc_mariko();
/* Set ACTIVE_CLUSER to FAST. */
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
/* Enable VddCpu. */
cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
if (!(car->pllx_base & 0x40000000)) {
car->pllx_misc3 &= 0xFFFFFFF7;
udelay(2);
@ -127,7 +133,7 @@ void cluster_boot_cpu0(uint32_t entry) {
car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
car->pllx_base = 0x40404E02;
}
while (!(car->pllx_base & 0x8000000)) {
/* Wait. */
}
@ -139,7 +145,7 @@ void cluster_boot_cpu0(uint32_t entry) {
car->cclk_brst_pol = 0x20008888;
car->super_cclk_div = 0x80000000;
car->clk_enb_v_set = 1;
/* Reboot CORESIGHT. */
clkrst_reboot(CARDEVICE_CORESIGHT);
@ -148,10 +154,10 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Enable CPU rail. */
cluster_pmc_enable_partition(1, 0);
/* Enable cluster 0 non-CPU. */
cluster_pmc_enable_partition(0x8000, 15);
/* Enable CE0. */
cluster_pmc_enable_partition(0x4000, 14);
@ -166,7 +172,7 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Set reset vector. */
SB_AA64_RESET_LOW_0 = (entry | 1);
SB_AA64_RESET_HIGH_0 = 0;
/* Non-secure reset vector write disable. */
SB_CSR_0 = 2;
(void)SB_CSR_0;
@ -174,15 +180,15 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
/* NOTE: This breaks Exosphère. */
/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
/* Clear MSELECT reset. */
rst_disable(CARDEVICE_MSELECT);
if (!is_mariko) {
/* Clear NONCPU reset. */
car->rst_cpug_cmplx_clr = 0x20000000;
}
/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
car->rst_cpug_cmplx_clr = 0x41010001;
}