mirrors/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere.git synced 2024-12-18 08:22:04 +00:00
Code Issues Releases Activity

kern: improve single-step around user-exception entry

Browse source
This commit is contained in:
Michael Scire 2021-07-27 15:09:36 -07:00
parent 325ae30067
commit 999318838f
2 changed files with 11 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
libraries/libmesosphere/source/arch/arm64/kern_exception_handlers.cpp
View file

@ -109,13 +109,9 @@ namespace ams::kern::arch::arm64 {
break;
}
/* If we should, clear the thread's state as single-step. */
/* In the event that we return from this exception, we want SPSR.SS set so that we advance an instruction if single-stepping. */
#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
if (AMS_UNLIKELY(GetCurrentThread().IsSingleStep())) {
GetCurrentThread().ClearSingleStep();
cpu::MonitorDebugSystemControlRegisterAccessor().SetSoftwareStep(false).Store();
cpu::EnsureInstructionConsistency();
}
context->psr |= (1ul << 21);
#endif
/* If we should process the user exception (and it's not a breakpoint), try to enter. */
@ -224,6 +220,15 @@ namespace ams::kern::arch::arm64 {
}
}
/* If we should, clear the thread's state as single-step. */
#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
if (AMS_UNLIKELY(GetCurrentThread().IsSingleStep())) {
GetCurrentThread().ClearSingleStep();
cpu::MonitorDebugSystemControlRegisterAccessor().SetSoftwareStep(false).Store();
cpu::EnsureInstructionConsistency();
}
#endif
{
/* Collect additional information based on the ec. */
ams::svc::DebugException exception;

5
mesosphere/kernel/source/arch/arm64/kern_exception_handlers_asm.s
View file

@ -217,11 +217,6 @@ _ZN3ams4kern4arch5arm6430EL0SynchronousExceptionHandlerEv:
ldp x21, x22, [sp, #(EXCEPTION_CONTEXT_PC_PSR)]
ldr x23, [sp, #(EXCEPTION_CONTEXT_TPIDR)]
#if defined(MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP)
/* Since we're returning from an exception, set SPSR.SS so that we advance an instruction if single-stepping. */
orr x22, x22, #(1 << 21)
#endif
msr sp_el0, x20
msr elr_el1, x21
msr spsr_el1, x22