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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-15 00:16:48 +00:00
thermosphere: fix x18 init, etc.
This commit is contained in:
parent
3fa9133814
commit
a11b0b6e0e
5 changed files with 35 additions and 26 deletions
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@ -133,7 +133,7 @@ all: $(BUILD)
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ifeq ($(PLATFORM), qemu)
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ifeq ($(PLATFORM), qemu)
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-bios bl1.bin -d unimp,int -semihosting-config enable,target=native -serial mon:stdio
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-bios bl1.bin -d unimp -semihosting-config enable,target=native -serial mon:stdio
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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@ -16,9 +16,23 @@
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#include "core_ctx.h"
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#include "core_ctx.h"
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// start.s
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extern uintptr_t g_initialKernelEntrypoint;
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// Prevents it from being put in BSS
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CoreCtx g_coreCtxs[4] = {
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CoreCtx g_coreCtxs[4] = {
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{ .coreId = 0 },
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{ .coreId = 0 },
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{ .coreId = 1 },
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{ .coreId = 1 },
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{ .coreId = 2 },
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{ .coreId = 2 },
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{ .coreId = 3 },
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{ .coreId = 3 },
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};
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};
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void coreCtxInit(u32 coreId, bool isColdbootCore, u64 argument)
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{
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currentCoreCtx = &g_coreCtxs[coreId];
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currentCoreCtx->isColdbootCore = isColdbootCore;
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currentCoreCtx->kernelArgument = argument;
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if (isColdbootCore) {
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currentCoreCtx->kernelEntrypoint = g_initialKernelEntrypoint;
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}
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}
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@ -21,8 +21,10 @@ typedef struct CoreCtx {
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u64 kernelArgument;
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u64 kernelArgument;
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uintptr_t kernelEntrypoint;
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uintptr_t kernelEntrypoint;
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u32 coreId; // @0x10
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u32 coreId; // @0x10
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bool isColdBootCore; // @0x14
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bool isColdbootCore; // @0x14
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} CoreCtx;
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} CoreCtx;
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extern CoreCtx g_coreCtxs[4];
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extern CoreCtx g_coreCtxs[4];
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register CoreCtx *currentCoreCtx asm("x18");
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register CoreCtx *currentCoreCtx asm("x18");
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void coreCtxInit(u32 coreId, bool isColdbootCore, u64 argument);
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@ -13,7 +13,7 @@ static void loadKernelViaSemihosting(void)
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uintptr_t buf = (uintptr_t)__start__ + (1<<20);
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uintptr_t buf = (uintptr_t)__start__ + (1<<20);
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long handle = -1, ret;
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long handle = -1, ret;
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DEBUG("Loading kernel via semihosting file I/O... ");
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DEBUG("Loading kernel via semihosted file I/O... ");
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handle = semihosting_file_open("test_kernel.bin", FOPEN_MODE_RB);
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handle = semihosting_file_open("test_kernel.bin", FOPEN_MODE_RB);
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if (handle < 0) {
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if (handle < 0) {
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DEBUG("failed to open file (%ld)!\n", handle);
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DEBUG("failed to open file (%ld)!\n", handle);
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@ -25,7 +25,7 @@ static void loadKernelViaSemihosting(void)
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panic();
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panic();
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}
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}
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DEBUG("OK!");
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DEBUG("OK!\n");
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semihosting_file_close(handle);
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semihosting_file_close(handle);
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currentCoreCtx->kernelEntrypoint = buf;
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currentCoreCtx->kernelEntrypoint = buf;
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}
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}
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@ -34,9 +34,9 @@ int main(void)
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{
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{
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enableTraps();
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enableTraps();
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if (currentCoreCtx->isColdBootCore) {
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if (currentCoreCtx->isColdbootCore) {
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uartInit(115200);
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uartInit(115200);
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DEBUG("Hello from Thermosphere!\n");
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DEBUG("EL2: core %u reached main first!\n", currentCoreCtx->coreId);
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if (currentCoreCtx->kernelEntrypoint == 0) {
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if (currentCoreCtx->kernelEntrypoint == 0) {
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if (semihosting_connection_supported()) {
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if (semihosting_connection_supported()) {
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loadKernelViaSemihosting();
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loadKernelViaSemihosting();
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@ -48,7 +48,7 @@ int main(void)
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}
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}
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}
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}
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else {
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else {
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DEBUG("Core %u booted\n", currentCoreCtx->coreId);
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DEBUG("EL2: core %u reached main!\n", currentCoreCtx->coreId);
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}
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}
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return 0;
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return 0;
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@ -23,7 +23,8 @@ _start:
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b start
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b start
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b start2
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b start2
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_initialKernelEntrypoint:
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.global g_initialKernelEntrypoint
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g_initialKernelEntrypoint:
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.quad 0
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.quad 0
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start:
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start:
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@ -58,35 +59,27 @@ _startCommon:
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dsb sy
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dsb sy
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isb
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isb
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mov x2, x0
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// Get core ID
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// Get core ID
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// Ensure Aff0 is 4-1 at most (4 cores), and that Aff1, 2 and 3 are 0 (1 cluster only)
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// Ensure Aff0 is 4-1 at most (4 cores), and that Aff1, 2 and 3 are 0 (1 cluster only)
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mrs x10, mpidr_el1
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mrs x0, mpidr_el1
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and x10, x10, #0x00FFFFFF // Aff0 to 2
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tst x0, #(0xFF << 32)
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and x10, x10, #(0xFF << 32) // Aff3
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bne .
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cmp x10, #4
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and x0, x0, #0x00FFFFFF // Aff0 to 2
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cmp x0, #4
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bhs .
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bhs .
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// Set tmp stack (__stacks_top__ is aligned)
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// Set tmp stack (__stacks_top__ is aligned)
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adrp x8, __stacks_top__
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adrp x8, __stacks_top__
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lsl x9, x10, #10
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lsl x9, x0, #10
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sub sp, x8, x9
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sub sp, x8, x9
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// Set up x18
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// Set up x18
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adrp x18, g_coreCtxs
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mov w1, w19
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add x18, x18, #:lo12:g_coreCtxs
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bl coreCtxInit
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add x18, x18, x10, lsl #3
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stp x18, xzr, [sp, #-0x10]!
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stp x18, xzr, [sp, #-0x10]!
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strb w19, [x18, #0x14] // isColdbootCore
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// Store entrypoint if first core
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cbz x19, _store_arg
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ldr x8, _initialKernelEntrypoint
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str x8, [x18, #8]
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_store_arg:
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str x0, [x18, #0]
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// Don't call init array to save space?
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// Don't call init array to save space?
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// Clear BSS & call main for the first core executing this code
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// Clear BSS & call main for the first core executing this code
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cbz x19, _jump_to_main
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cbz x19, _jump_to_main
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