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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-09 21:51:45 +00:00
Add some more MMIO, smcCpuOn
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parent
5c24f58402
commit
a800c3c2e7
10 changed files with 204 additions and 3 deletions
56
exosphere/cpu_context.c
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56
exosphere/cpu_context.c
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@ -0,0 +1,56 @@
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#include <stdint.h>
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#include "utils.h"
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#include "pmc.h"
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saved_cpu_context_t g_cpu_contexts[NUM_CPU_CORES] = {0};
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void set_core_entrypoint_and_context_id(uint32_t core, uint64_t entrypoint_addr, uint64_t context_id) {
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g_cpu_contexts[core].ELR_EL3 = entrypoint_addr;
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g_cpu_contexts[core].context_id = context_id;
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}
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uint32_t cpu_on(uint32_t core, uint64_t entrypoint_addr, uint64_t context_id) {
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/* Is core valid? */
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if (core >= NUM_CPU_CORES) {
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return 0xFFFFFFFE;
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}
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/* Is core already on? */
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if (g_cpu_contexts[core].is_active) {
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return 0xFFFFFFFC;
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}
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set_core_entrypoint_and_context_id(core, entrypoint_addr, context_id);
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const uint32_t status_masks[NUM_CPU_CORES] = {0x4000, 0x200, 0x400, 0x800};
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const uint32_t toggle_vals[NUM_CPU_CORES] = {0xE, 0x9, 0xA, 0xB};
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/* Check if we're already in the correct state. */
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if ((APBDEV_PMC_PWRGATE_STATUS_0 & status_masks[core]) != status_masks[core]) {
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uint32_t counter = 5001;
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/* Poll the start bit until 0 */
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while (APBDEV_PMC_PWRGATE_TOGGLE_0 & 0x100) {
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wait(1);
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counter--;
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if (counter < 1) {
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return 0;
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}
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}
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/* Program PWRGATE_TOGGLE with the START bit set to 1, selecting CE[N] */
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APBDEV_PMC_PWRGATE_TOGGLE_0 = toggle_vals[core] | 0x100;
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/* Poll until we're in the correct state. */
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counter = 5001;
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while (counter > 0) {
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if ((APBDEV_PMC_PWRGATE_STATUS_0 & status_masks[core]) == status_masks[core]) {
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break;
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}
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wait(1);
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counter--;
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}
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}
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return 0;
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}
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54
exosphere/cpu_context.h
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54
exosphere/cpu_context.h
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@ -0,0 +1,54 @@
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#ifndef EXOSPHERE_CPU_CTX_H
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#define EXOSPHERE_CPU_CTX_H
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#include <stdint.h>
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/* Exosphere CPU Management functionality. */
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typedef struct {
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uint64_t context_id;
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uint64_t ELR_EL3;
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int is_active;
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int is_saved;
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uint32_t OSDTRRX_EL1;
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uint32_t OSDTRTX_EL1;
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uint32_t MDSCR_EL1;
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uint32_t OSECCR_EL1;
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uint32_t MDCCINT_EL1;
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uint32_t DBGCLAIMCLR_EL1;
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uint32_t DBGVCR32_EL2;
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uint32_t SDER32_EL3;
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uint32_t MDCR_EL2;
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uint32_t MDCR_EL3;
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uint64_t DBGBVR0_EL1;
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uint64_t DBGBCR0_EL1;
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uint64_t DBGBVR1_EL1;
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uint64_t DBGBCR1_EL1;
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uint64_t DBGBVR2_EL1;
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uint64_t DBGBCR2_EL1;
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uint64_t DBGBVR3_EL1;
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uint64_t DBGBCR3_EL1;
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uint64_t DBGBVR4_EL1;
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uint64_t DBGBCR4_EL1;
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uint64_t DBGBVR5_EL1;
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uint64_t DBGBCR5_EL1;
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uint64_t DBGWVR0_EL1;
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uint64_t DBGWCR0_EL1;
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uint64_t DBGWVR1_EL1;
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uint64_t DBGWCR1_EL1;
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uint64_t DBGWVR2_EL1;
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uint64_t DBGWCR2_EL1;
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uint64_t DBGWVR3_EL1;
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uint64_t DBGWCR3_EL1;
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} saved_cpu_context_t;
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#define NUM_CPU_CORES 4
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void set_core_entrypoint_and_context_id(uint64_t entrypoint_addr, uint64_t context_id);
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uint32_t cpu_on(uint32_t core, uint64_t entrypoint_addr, uint64_t context_id);
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uint32_t cpu_off(void);
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uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint_addr, uint64_t context_id);
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#endif
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11
exosphere/pmc.c
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11
exosphere/pmc.c
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@ -0,0 +1,11 @@
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#include "pmc.h"
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volatile void *g_pmc_registers = NULL;
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void set_pmc_address(void *pmc_base) {
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g_pmc_registers = pmc_base;
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}
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inline void *get_pmc_address(void) {
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return g_pmc_registers;
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}
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14
exosphere/pmc.h
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14
exosphere/pmc.h
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#ifndef EXOSPHERE_PMC_H
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#define EXOSPHERE_PMC_H
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#include <stdint.h>
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/* Exosphere register definitions for the Tegra X1 PMC. */
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void set_pmc_address(void *pmc_base);
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void *get_pmc_address(void); /* This is inlined in pmc.c */
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#define APBDEV_PMC_PWRGATE_TOGGLE_0 (*((volatile uint32_t *)(get_pmc_address() + 0x430)))
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#define APBDEV_PMC_PWRGATE_STATUS_0 (*((volatile uint32_t *)(get_pmc_address() + 0x438)))
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#endif
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@ -7,7 +7,7 @@ void trigger_se_rsa_op(void *buf, unsigned int size);
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void trigger_se_aes_op(unsigned int op, char *dst, unsigned int dst_size, const unsigned char *src, unsigned int src_size);
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/* Globals for driver. */
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security_engine_t *g_security_engine;
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volatile security_engine_t *g_security_engine;
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unsigned int (*g_se_callback)(void);
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@ -19,6 +19,11 @@ void set_security_engine_address(security_engine_t *security_engine) {
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g_security_engine = security_engine;
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}
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/* Get the global security engine pointer. */
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security_engine_t *get_security_engine_address(void) {
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return g_security_engine;
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}
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void set_security_engine_callback(unsigned int (*callback)(void)) {
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if (callback == NULL || g_se_callback != NULL) {
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panic();
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@ -92,7 +92,8 @@ typedef struct security_engine {
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void set_security_engine_address(void *security_engine);
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void set_security_engine_address(security_engine_t *security_engine);
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security_engine_t *get_security_engine_address(void);
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void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags);
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void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags);
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@ -1,6 +1,7 @@
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#include <stdint.h>
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#include "utils.h"
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#include "cpu_context.h"
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#include "smc_api.h"
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#include "smc_user.h"
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#include "se.h"
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@ -223,5 +224,23 @@ uint32_t smc_get_result(smc_args_t *) {
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}
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uint32_t smc_load_aes_key(smc_args_t *args) {
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smc_wrapper_sync(args, user_load_aes_key);
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return smc_wrapper_sync(args, user_load_aes_key);
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}
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uint32_t smc_cpu_on(smc_args_t *args) {
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return cpu_on((uint32_t)args->X[1], args->X[2], args->X[3]);
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}
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uint32_t smc_cpu_off(smc_args_t *args) {
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return cpu_off();
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}
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/* Wrapper for cpu_suspend */
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uint32_t cpu_suspend_wrapper(smc_args_t *args) {
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return cpu_suspend(args->X[1], args->X[2], args->X[3]);
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}
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uint32_t smc_cpu_suspend(smc_args_t *args) {
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return smc_wrapper_sync(args, cpu_suspend_wrapper);
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}
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18
exosphere/timers.c
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18
exosphere/timers.c
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#include "timers.h"
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volatile void *g_timer_registers = NULL;
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void set_timer_address(void *timer_base) {
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g_timer_registers = timer_base;
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}
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inline void *get_timer_address(void) {
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return g_timer_registers;
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}
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void wait(uint32_t microseconds) {
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uint32_t old_time = TIMERUS_CNTR_1US_0;
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while (TIMERUS_CNTR_1US_0 - old_time <= result) {
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/* Spin-lock. */
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}
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}
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15
exosphere/timers.h
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15
exosphere/timers.h
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#ifndef EXOSPHERE_TIMERS_H
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#define EXOSPHERE_TIMERS_H
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#include <stdint.h>
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/* Exosphere driver for the Tegra X1 Timers. */
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void set_timer_address(void *timer_base);
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void *get_timer_address(void); /* This is inlined in timers.c */
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#define TIMERUS_CNTR_1US_0 (*((volatile uint32_t *)(get_timer_address() + 0x10)))
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void wait(uint32_t microseconds);
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#endif
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#ifndef EXOSPHERE_UTILS_H
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#define EXOSPHERE_UTILS_H
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#include <stdint.h>
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void panic(void);
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unsigned int read32le(const unsigned char *dword, unsigned int offset);
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unsigned int read32be(const unsigned char *dword, unsigned int offset);
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static inline uint32_t get_core_id(void) {
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uint32_t core_id;
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asm volatile("mrs %0, MPIDR_EL1" : "=r"(core_id));
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return core_id;
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}
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#endif
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