mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-18 08:22:04 +00:00
kern: implement revised IPI/SGI semantics
This commit is contained in:
parent
7454507467
commit
bb0be4de8e
9 changed files with 103 additions and 20 deletions
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@ -188,6 +188,7 @@ namespace ams::kern::arch::arm64::cpu {
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/* Synchronization helpers. */
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NOINLINE void SynchronizeAllCores();
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void SynchronizeCores(u64 core_mask);
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/* Cache management helpers. */
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void StoreCacheForInit(void *addr, size_t size);
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@ -21,11 +21,12 @@ namespace ams::kern::arch::arm64 {
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enum KInterruptName : s32 {
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/* SGIs */
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KInterruptName_ThreadTerminate = 4,
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KInterruptName_CacheOperation = 5,
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KInterruptName_Scheduler = 6,
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KInterruptName_ThreadTerminate = 0,
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KInterruptName_CacheOperation = 1,
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KInterruptName_Scheduler = 2,
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KInterruptName_CoreBarrier = 3,
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KInterruptName_PerformanceCounter = 8,
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KInterruptName_PerformanceCounter = 4,
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/* PPIs */
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#if defined(ATMOSPHERE_BOARD_NINTENDO_NX)
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@ -30,6 +30,7 @@
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#endif
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//#define MESOSPHERE_BUILD_FOR_TRACING
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//#define MESOSPHERE_ENABLE_PERFORMANCE_COUNTER
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#define MESOSPHERE_ENABLE_PANIC_REGISTER_DUMP
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#define MESOSPHERE_ENABLE_HARDWARE_SINGLE_STEP
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@ -184,6 +184,7 @@ namespace ams::kern {
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svc::SvcAccessFlagSet m_svc_access_flags;
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InterruptFlagSet m_irq_access_flags;
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u64 m_core_mask;
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u64 m_phys_core_mask;
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u64 m_priority_mask;
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util::BitPack32 m_debug_capabilities;
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s32 m_handle_table_size;
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@ -227,7 +228,7 @@ namespace ams::kern {
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Result SetCapabilities(const u32 *caps, s32 num_caps, KProcessPageTable *page_table);
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Result SetCapabilities(svc::KUserPointer<const u32 *> user_caps, s32 num_caps, KProcessPageTable *page_table);
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public:
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constexpr explicit KCapabilities(util::ConstantInitializeTag) : m_svc_access_flags{}, m_irq_access_flags{}, m_core_mask{}, m_priority_mask{}, m_debug_capabilities{0}, m_handle_table_size{}, m_intended_kernel_version{}, m_program_type{} { /* ... */ }
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constexpr explicit KCapabilities(util::ConstantInitializeTag) : m_svc_access_flags{}, m_irq_access_flags{}, m_core_mask{}, m_phys_core_mask{}, m_priority_mask{}, m_debug_capabilities{0}, m_handle_table_size{}, m_intended_kernel_version{}, m_program_type{} { /* ... */ }
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KCapabilities() { /* ... */ }
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Result Initialize(const u32 *caps, s32 num_caps, KProcessPageTable *page_table);
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@ -236,6 +237,7 @@ namespace ams::kern {
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static Result CheckCapabilities(svc::KUserPointer<const u32 *> user_caps, s32 num_caps);
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constexpr u64 GetCoreMask() const { return m_core_mask; }
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constexpr u64 GetPhysicalCoreMask() const { return m_phys_core_mask; }
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constexpr u64 GetPriorityMask() const { return m_priority_mask; }
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constexpr s32 GetHandleTableSize() const { return m_handle_table_size; }
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@ -160,6 +160,7 @@ namespace ams::kern {
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constexpr State GetState() const { return m_state; }
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constexpr u64 GetCoreMask() const { return m_capabilities.GetCoreMask(); }
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constexpr u64 GetPhysicalCoreMask() const { return m_capabilities.GetPhysicalCoreMask(); }
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constexpr u64 GetPriorityMask() const { return m_capabilities.GetPriorityMask(); }
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constexpr s32 GetIdealCoreId() const { return m_ideal_core_id; }
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@ -67,6 +67,16 @@ namespace ams::kern {
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return mask;
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}();
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static constexpr inline u64 ConvertVirtualCoreMaskToPhysical(u64 v_core_mask) {
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u64 p_core_mask = 0;
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while (v_core_mask != 0) {
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const u64 next = __builtin_ctzll(v_core_mask);
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v_core_mask &= ~(static_cast<u64>(1) << next);
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p_core_mask |= (static_cast<u64>(1) << cpu::VirtualToPhysicalCoreMap[next]);
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}
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return p_core_mask;
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}
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}
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static_assert(cpu::NumCores <= cpu::NumVirtualCores);
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@ -23,6 +23,14 @@ namespace ams::kern::arch::arm64::cpu {
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namespace {
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ALWAYS_INLINE void SetEventLocally() {
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__asm__ __volatile__("sevl" ::: "memory");
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}
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ALWAYS_INLINE void WaitForEvent() {
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__asm__ __volatile__("wfe" ::: "memory");
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}
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class KScopedCoreMigrationDisable {
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public:
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ALWAYS_INLINE KScopedCoreMigrationDisable() { GetCurrentThread().DisableCoreMigration(); }
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@ -82,6 +90,51 @@ namespace ams::kern::arch::arm64::cpu {
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}
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};
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class KCoreBarrierInterruptHandler : public KInterruptHandler {
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private:
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util::Atomic<u64> m_target_cores;
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KSpinLock m_lock;
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public:
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constexpr KCoreBarrierInterruptHandler() : KInterruptHandler(), m_target_cores(0), m_lock() { /* ... */ }
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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m_target_cores &= ~(1ul << GetCurrentCoreId());
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return nullptr;
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}
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void SynchronizeCores(u64 core_mask) {
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/* Disable dispatch while we synchronize. */
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KScopedDisableDispatch dd;
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/* Acquire exclusive access to ourselves. */
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KScopedSpinLock lk(m_lock);
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/* If necessary, force synchronization with other cores. */
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if (const u64 other_cores_mask = core_mask & ~(1ul << GetCurrentCoreId()); other_cores_mask != 0) {
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/* Send an interrupt to the other cores. */
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m_target_cores = other_cores_mask;
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cpu::DataSynchronizationBarrierInnerShareable();
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Kernel::GetInterruptManager().SendInterProcessorInterrupt(KInterruptName_CoreBarrier, other_cores_mask);
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/* Wait for all cores to acknowledge. */
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{
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u64 v;
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__asm__ __volatile__("ldaxr %[v], %[p]\n"
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"cbz %[v], 1f\n"
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"0:\n"
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"wfe\n"
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"ldaxr %[v], %[p]\n"
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"cbnz %[v], 0b\n"
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"1:\n"
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: [v]"=&r"(v)
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: [p]"Q"(*reinterpret_cast<u64 *>(std::addressof(m_target_cores)))
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: "memory");
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}
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}
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}
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};
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class KCacheHelperInterruptHandler : public KInterruptHandler {
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private:
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static constexpr s32 ThreadPriority = 8;
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@ -215,7 +268,11 @@ namespace ams::kern::arch::arm64::cpu {
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/* Instances of the interrupt handlers. */
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constinit KThreadTerminationInterruptHandler g_thread_termination_handler;
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constinit KCacheHelperInterruptHandler g_cache_operation_handler;
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constinit KCoreBarrierInterruptHandler g_core_barrier_handler;
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#if defined(MESOSPHERE_ENABLE_PERFORMANCE_COUNTER)
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constinit KPerformanceCounterInterruptHandler g_performance_counter_handler[cpu::NumCores];
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#endif
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/* Expose this as a global, for asm to use. */
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constinit s32 g_all_core_sync_count;
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@ -296,14 +353,6 @@ namespace ams::kern::arch::arm64::cpu {
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}
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}
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ALWAYS_INLINE void SetEventLocally() {
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__asm__ __volatile__("sevl" ::: "memory");
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}
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ALWAYS_INLINE void WaitForEvent() {
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__asm__ __volatile__("wfe" ::: "memory");
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}
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ALWAYS_INLINE Result InvalidateDataCacheRange(uintptr_t start, uintptr_t end) {
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MESOSPHERE_ASSERT(util::IsAligned(start, DataCacheLineSize));
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MESOSPHERE_ASSERT(util::IsAligned(end, DataCacheLineSize));
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@ -338,6 +387,11 @@ namespace ams::kern::arch::arm64::cpu {
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}
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void SynchronizeCores(u64 core_mask) {
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/* Request a core barrier interrupt. */
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g_core_barrier_handler.SynchronizeCores(core_mask);
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}
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void StoreCacheForInit(void *addr, size_t size) {
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/* Store the data cache for the specified range. */
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const uintptr_t start = util::AlignDown(reinterpret_cast<uintptr_t>(addr), DataCacheLineSize);
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@ -446,9 +500,15 @@ namespace ams::kern::arch::arm64::cpu {
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/* Bind all handlers to the relevant interrupts. */
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Kernel::GetInterruptManager().BindHandler(std::addressof(g_cache_operation_handler), KInterruptName_CacheOperation, core_id, KInterruptController::PriorityLevel_High, false, false);
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Kernel::GetInterruptManager().BindHandler(std::addressof(g_thread_termination_handler), KInterruptName_ThreadTerminate, core_id, KInterruptController::PriorityLevel_Scheduler, false, false);
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Kernel::GetInterruptManager().BindHandler(std::addressof(g_core_barrier_handler), KInterruptName_CoreBarrier, core_id, KInterruptController::PriorityLevel_Scheduler, false, false);
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/* If we should, enable user access to the performance counter registers. */
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if (KTargetSystem::IsUserPmuAccessEnabled()) { SetPmUserEnrEl0(1ul); }
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/* If we should, enable the kernel performance counter interrupt handler. */
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#if defined(MESOSPHERE_ENABLE_PERFORMANCE_COUNTER)
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Kernel::GetInterruptManager().BindHandler(std::addressof(g_performance_counter_handler[core_id]), KInterruptName_PerformanceCounter, core_id, KInterruptController::PriorityLevel_Timer, false, false);
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#endif
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}
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void SynchronizeAllCores() {
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@ -27,7 +27,11 @@ namespace ams::kern {
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m_program_type = 0;
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/* Initial processes may run on all cores. */
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m_core_mask = cpu::VirtualCoreMask;
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constexpr u64 VirtMask = cpu::VirtualCoreMask;
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constexpr u64 PhysMask = cpu::ConvertVirtualCoreMaskToPhysical(VirtMask);
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m_core_mask = VirtMask;
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m_phys_core_mask = PhysMask;
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/* Initial processes may use any user priority they like. */
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m_priority_mask = ~0xFul;
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@ -60,7 +64,7 @@ namespace ams::kern {
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Result KCapabilities::SetCorePriorityCapability(const util::BitPack32 cap) {
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/* We can't set core/priority if we've already set them. */
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R_UNLESS(m_core_mask == 0, svc::ResultInvalidArgument());
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R_UNLESS(m_core_mask == 0, svc::ResultInvalidArgument());
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R_UNLESS(m_priority_mask == 0, svc::ResultInvalidArgument());
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/* Validate the core/priority. */
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@ -81,6 +85,9 @@ namespace ams::kern {
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}
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MESOSPHERE_ASSERT((m_core_mask & cpu::VirtualCoreMask) == m_core_mask);
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/* Set physical core mask. */
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m_phys_core_mask = cpu::ConvertVirtualCoreMaskToPhysical(m_core_mask);
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/* Set priority mask. */
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for (auto prio = min_prio; prio <= max_prio; prio++) {
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m_priority_mask |= (1ul << prio);
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@ -481,12 +481,16 @@ namespace ams::kern {
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/* Ensure that the thread is not executing on any core. */
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if (m_parent != nullptr) {
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/* Wait for the thread to not be current on any core. */
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for (size_t i = 0; i < cpu::NumCores; ++i) {
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KThread *core_thread;
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do {
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core_thread = Kernel::GetScheduler(i).GetSchedulerCurrentThread();
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} while (core_thread == this);
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}
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/* Ensure that all cores are synchronized at this point. */
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cpu::SynchronizeCores(m_parent->GetPhysicalCoreMask());
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}
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/* Close the thread. */
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@ -724,11 +728,7 @@ namespace ams::kern {
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}
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/* Translate the virtual affinity mask to a physical one. */
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while (v_affinity_mask != 0) {
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const u64 next = __builtin_ctzll(v_affinity_mask);
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v_affinity_mask &= ~(1ul << next);
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p_affinity_mask |= (1ul << cpu::VirtualToPhysicalCoreMap[next]);
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}
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p_affinity_mask = cpu::ConvertVirtualCoreMaskToPhysical(v_affinity_mask);
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/* If we haven't disabled migration, perform an affinity change. */
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if (m_num_core_migration_disables == 0) {
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